include/ufs/ufshcd.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4  * Copyright (C) 2011-2013 Samsung India Software Operations
5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
21 #include <linux/dma-direction.h>
65  * struct uic_command - UIC command structure
89 /* Host <-> Device UniPro Link state */
97 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
98 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
100 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
102 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
104 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
105 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
107 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
109 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
113 	((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
115 	((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
117 	((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
119 	((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
121 	((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
123 	((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
125 	((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
127 	((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
152  * struct ufshcd_lrb - local reference block
171  * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
191 	u8 lun; /* UPIU LUN id field is only 8-bit wide */
206  * struct ufs_query_req - parameters for building a query request
216  * struct ufs_query_resp - UPIU QUERY
225  * struct ufs_query - holds relevant data structures for query request
237  * struct ufs_dev_cmd - all assosiated fields with device management commands
238  * @type: device management command type - Query, NOP OUT
251  * struct ufs_clk_info - UFS clock related info
252  * @list: list headed by hba->clk_list_head
294  * struct ufs_hba_variant_ops - variant specific callbacks
304  *                     variant specific Uni-Pro initialization.
306  *                       to allow variant specific Uni-Pro initialization.
388  * struct ufs_clk_gating - UFS clock gating related info
420  * struct ufs_clk_scaling - UFS clock scaling related data
422  * devfreq ->target() function is called then schedule "suspend_work" to
462  * struct ufs_event_hist - keeps history of errors
476  * struct ufs_stats - keeps usage/err statistics
480  *		reset this after link-startup.
495  * enum ufshcd_state - UFS host controller state
587 	 * auto-hibernate capability but it doesn't work.
592 	 * This quirk needs to disable manual flush for write booster
621 	 * auto-hibernate capability but it's FASTAUTO only.
666 	 * This capability allows the device auto-bkops to be always enabled
682 	 * This capability allows the host controller driver to turn-on
704 	 * support device hardware reset via the hba->device_reset() callback,
749  * struct ufshcd_res_info_t - MCQ related resource regions
773  * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
794  * struct ufs_hba - per adapter private structure
811  * @ahit: value of Auto-Hibernate Idle Timer register.
863  * @vreg_info: UFS device voltage regulator information
880  * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
941 	/* Auto-Hibernate Idle Timer register value */
1074  * struct ufs_hw_queue - per hardware queue structure
1115 	return hba->mcq_enabled;
1121 	return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1127 	return hba->sg_entry_size;
1133 	hba->sg_entry_size = sg_entry_size;
1153 	return hba->caps & UFSHCD_CAP_CLK_GATING;
1157 	return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1161 	return hba->caps & UFSHCD_CAP_CLK_SCALING;
1165 	return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1169 	return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1174 	return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1175 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1181 		  (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1186 	return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1187 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1192 	return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1197 	return hba->caps & UFSHCD_CAP_WB_EN;
1202 	return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1206 	writel((val), (hba)->mcq_base + (reg))
1208 	readl((hba)->mcq_base + (reg))
1211 	writel_relaxed((val), (hba)->mcq_base + (reg))
1213 	readl_relaxed((hba)->mcq_base + (reg))
1216 	writel((val), (hba)->mmio_base + (reg))
1218 	readl((hba)->mmio_base + (reg))
1221  * ufshcd_rmwl - perform read/modify/write for a controller register
1261  * ufshcd_set_variant - set variant specific data to the hba
1268 	hba->priv = variant;
1272  * ufshcd_get_variant - get variant specific data from the hba
1278 	return hba->priv;
1352 	return (pwr_info->pwr_rx == FAST_MODE ||
1353 		pwr_info->pwr_rx == FASTAUTO_MODE) &&
1354 		(pwr_info->pwr_tx == FAST_MODE ||
1355 		pwr_info->pwr_tx == FASTAUTO_MODE);
1397 	if (hba->vops && hba->vops->init)
1398 		return hba->vops->init(hba);
1405 	if (hba->vops && hba->vops->phy_initialization)
1406 		return hba->vops->phy_initialization(hba);