Lines Matching +full:max +full:- +full:link +full:- +full:speed
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
18 * The HyperTransport I/O Link Specification
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
123 /* 0x35-0x3b are reserved */
129 /* Header type 1 (PCI-to-PCI bridges) */
157 /* 0x35-0x3b is reserved */
159 /* 0x3c-0x3d are same as for htype 0 */
190 /* 0x3c-0x3d are same as for htype 0 */
198 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
204 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
205 /* 0x48-0x7f reserved */
216 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
218 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
221 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
223 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
226 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
255 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
271 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
273 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
282 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
294 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
310 #define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */
311 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
315 #define PCI_MSI_DATA_32 0x08 /* 16 bits of data for 32-bit devices */
316 #define PCI_MSI_MASK_32 0x0c /* Mask bits register for 32-bit devices */
317 #define PCI_MSI_PENDING_32 0x10 /* Pending intrs for 32-bit devices */
318 #define PCI_MSI_DATA_64 0x0c /* 16 bits of data for 64-bit devices */
319 #define PCI_MSI_MASK_64 0x10 /* Mask bits register for 64-bit devices */
320 #define PCI_MSI_PENDING_64 0x14 /* Pending intrs for 64-bit devices */
322 /* MSI-X registers (in MSI-X capability) */
326 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
336 /* MSI-X Table entry format (in memory mapped by a BAR) */
352 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
353 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
381 /* 0-5 map to BARs 0-5 respectively */
387 /* 9-14 map to VF BARs 0-5 respectively */
390 #define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
393 #define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
397 #define PCI_EA_P_VF_MEM 0x04 /* VF Non-Prefetch Memory */
398 #define PCI_EA_P_BRIDGE_MEM 0x05 /* Bridge Non-Prefetch Memory */
401 /* 0x08-0xfc reserved */
410 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
411 #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
413 /* PCI-X registers (Type 0 (non-bridge) devices) */
422 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
423 /* Max # of outstanding split transactions */
424 #define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */
425 #define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */
426 #define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */
427 #define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */
428 #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */
429 #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */
430 #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */
431 #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */
432 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
434 #define PCI_X_STATUS 4 /* PCI-X capabilities */
437 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
442 #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
443 #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
444 #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
453 /* PCI-X registers (Type 1 (bridge) devices) */
459 #define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */
481 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
482 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
496 #define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */
502 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
527 #define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */
532 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */
533 #define PCI_EXP_LNKCAP 0x0c /* Link Capabilities */
534 #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
541 #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
549 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
550 #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */
552 #define PCI_EXP_LNKCTL 0x10 /* Link Control */
557 #define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
558 #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
563 #define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
564 #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */
565 #define PCI_EXP_LNKSTA 0x12 /* Link Status */
566 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
567 #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
568 #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
569 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
570 #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
571 #define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */
572 #define PCI_EXP_LNKSTA_CLS_64_0GB 0x0006 /* Current Link Speed 64.0GT/s */
573 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
574 #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
575 #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
576 #define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */
577 #define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */
578 #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
579 #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
581 #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
582 #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
583 #define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
584 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints with link end here */
591 #define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
592 #define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
604 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
618 #define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
620 #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
630 #define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */
633 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
644 * Link Capabilities 2, Link Status 2, Link Control 2,
652 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
660 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
661 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
665 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
675 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 0x2c /* end of v2 EPs w/o link */
676 #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities 2 */
677 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
678 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */
679 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
680 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
681 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */
682 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */
684 #define PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */
686 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
687 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
688 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
689 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
690 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
691 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */
694 #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
695 #define PCI_EXP_LNKSTA2 0x32 /* Link Status 2 */
697 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link */
699 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
703 /* Extended Capabilities (PCI-X 2.0 and Express) */
712 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
713 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
715 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
718 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
719 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
738 #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
739 #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
751 #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
777 #define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
791 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
799 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
856 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
857 #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */
871 #define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */
872 #define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */
896 /* Alternative Routing-ID Interpretation */
910 #define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */
927 #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
928 #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
942 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
945 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
951 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
956 #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
993 #define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */
998 #define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
1015 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
1023 #define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
1073 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Supported */
1074 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Supported */
1082 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 /* PCI-PM L1.2 Enable */
1083 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 /* PCI-PM L1.1 Enable */
1093 /* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
1094 #define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-Specific Header1 */
1098 #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */
1101 /* Data Link Feature */
1103 #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
1128 /* DOE Data Object - note not actually registers */