Lines Matching +full:adc +full:- +full:sample +full:- +full:hold +full:- +full:time
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
41 // This is used to define hardware bit-fields (sub-registers) by combining
44 // The non-concatenating (_NC) variant should be used directly only for
45 // sub-registers that do not follow the <register>_<field> naming pattern.
55 // Macros for manipulating values of bit-fields declared using the above macros.
59 // single sub-register at a time.
62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
79 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
81 /* accessed. For non per-channel registers the */
103 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
112 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
113 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
117 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
134 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
139 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
143 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
144 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
145 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
146 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
148 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
161 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
162 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
167 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
175 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
180 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
181 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
184 SUB_REG(WC, SAMPLECOUNTER, 0x03FFFFC0) /* Sample periods elapsed since reset */
186 /* NOTE: Each channel takes 1/64th of a sample */
215 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
216 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
217 #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
219 /* they are not rate-locked to the external */
221 #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
223 /* the SPDIF V-bit indicates invalid audio */
225 #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
230 #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
237 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
238 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
248 /* the same async sample rate tracker (ZVIDEO) */
249 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
253 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
255 /* they are not rate-locked to the external */
267 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
271 // On Audigy, the MPU port moved to the 0x70-0x74 ptr registers
290 // card-specific info can be found in the emu_chip_details table.
291 // On E-MU cards the port is used as the interface to the FPGA.
300 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
312 /* of 1024 sample periods should be allowed */
314 #define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */
320 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
346 /* 0x00000000 2-channel output. */
347 /* 0x00000200 8-channel output. */
354 * bit 8: Record 8-channel in phase.
355 * bit 9: Playback 8-channel in phase.
356 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
383 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
388 // "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers
389 // "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view
392 // - The engine has 64 playback channels, also called voices. The channels
394 // - PCM samples are fetched into the cache; see description of CD0 below.
395 // - Samples are consumed at the rate CPF_CURRENTPITCH.
396 // - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8
397 // - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated
400 // - The value is multiplied by CVCF_CURRENTVOL.
401 // - The value goes through a filter with cutoff CVCF_CURRENTFILTER;
403 // - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2)
405 // multiplied by a per-send amount (*_FXSENDAMOUNT_*).
406 // The scaling of the send amounts is exponential-ish.
407 // - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*.
408 // - The pitch, volume, and filter cutoff can be modulated by two envelope
410 // - To avoid abrupt changes to the parameters (which may cause audible
417 // The somewhat non-obviously still meaningful ones are:
471 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
472 /* 8-bit samples are unsigned, 16-bit ones signed */
479 /* Auto-set from CPF_STEREO_MASK */
481 /* Auto-set from CCCA_8BITSELECT */
482 SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */
485 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
513 /* 0x8000-n == 666*n usec delay */
515 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
517 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
518 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
527 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
532 /* 0x8000-n == 666*n usec delay */
536 /* 0x8000-n == 666*n usec delay */
538 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
540 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
541 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
547 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
552 /* 0x8000-n == 666*n usec delay */
567 /* Signed 2's complement, +/- one octave peak extremes */
569 /* Signed 2's complement, +/- six octaves peak extremes */
574 /* Signed 2's complement, +/- one octave extremes */
576 /* Signed 2's complement, +/- three octave extremes */
580 /* Signed 2's complement, with +/- 12dB extremes */
586 /* Signed 2's complement, +/- one octave extremes */
591 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
599 // and hold the interleaved frames.
600 // The cache holds 64 frames, so the upper half is not used in 8-bit mode.
603 // The cache is filled from (CCCA_CURRADDR - CCR_CACHEINVALIDSIZE)
604 // into (CCR_READADDRESS - CCR_CACHEINVALIDSIZE).
606 // CCR_CACHEINVALIDSIZE below 8 (16-bit stereo), 16 (16-bit mono,
607 // 8-bit stereo), or 32 (8-bit mono). The actual transfers are pretty
620 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
628 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
629 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
630 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
631 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
632 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
633 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
634 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
635 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
636 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
637 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
638 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
639 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
640 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
645 /* 0x20-0x3f) to host memory. This mode of recording */
665 #define ADCBA 0x46 /* ADC buffer address register */
671 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
675 #define ADCBS 0x4a /* ADC buffer size register */
679 /* The following mask values define the size of the ADC, MIC and FX buffers in bytes */
720 // NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1)
721 #define CDCS 0x50 /* CD-ROM digital channel status register */
735 // NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
746 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
747 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
748 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
749 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
756 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
757 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
758 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
762 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
764 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
768 /* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */
784 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
785 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
795 // NOTE: 0x60,61,62: 64-bit
796 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
798 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
800 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
802 /* Assumes sample lock */
807 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
810 /* Note that these values can vary +/- by a small amount */
818 #define ADCIDX 0x64 /* ADC recording buffer index register */
830 /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */
859 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
860 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
864 #define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */
873 /* unclear if this sets the ADC rate as well. */
894 #define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */
895 #define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */
896 #define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */
897 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
941 /* E-MU Digital Audio System overview */
944 // - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2);
946 // - All physical PCM I/O is routed through an additional FPGA; the regular
948 // - The FPGA has a signal routing matrix, to connect each destination (output
950 // - The FPGA is controlled via Audigy's GPIO port, while sample data is
951 // transmitted via proprietary EMU32 serial links. On first-generation
952 // E-MU 1010 cards, Audigy's I2S inputs are also used for sample data.
953 // - The Audio/Micro Dock is attached to Hana via EDI, a "network" link.
954 // - The Audigy chip operates in slave mode; the clock is supplied by the FPGA.
955 // Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples),
957 // - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz
958 // sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels
960 // - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total
962 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
964 // can overlap with the Dock's ADC/DAC's high channels.
965 // - The code names are mentioned below and in the emu_chip_details table.
1036 #define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */
1037 #define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */
1039 #define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */
1040 #define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */
1064 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1065 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1066 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
1067 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
1068 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1094 /* 0x14 - 0x1f Unused R/W registers */
1119 // The actual code disagrees about the bit width of the registers -
1134 /* 0x30 - 0x3f Unused Read only registers */
1136 // The meaning of this is not clear; kX-project just calls it "lock" in some info-only code.
1144 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1145 * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock
1162 * 0x04, 0x00-0x07: Hana ADAT
1174 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1175 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1184 * 0x18-0x1f: Dock ADAT 0-7
1189 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1190 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1191 * 0x06-0x07: Not used
1195 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina
1201 * 0x04-0x07: Not used
1204 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1205 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1210 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1211 * 0x05-0x07: Not used
1214 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1215 * physical outputs of Hana, or outputs going to Alice2/Tina for capture -
1217 * a channel depends on the mixer control setting for each destination - see
1221 /* This channel is delayed by one sample. */
1317 * 0x00, 0x00-0x1f: Silence
1318 * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock
1321 * 0x08: Dock ADC 1 Left
1322 * 0x0c: Dock ADC 1 Right
1323 * 0x10: Dock ADC 2 Left
1324 * 0x14: Dock ADC 2 Right
1325 * 0x18: Dock ADC 3 Left
1326 * 0x1c: Dock ADC 3 Right
1327 * 0x02, 0x00: Hamoa ADC Left
1328 * 0x02, 0x01: Hamoa ADC Right
1329 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1330 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1331 * 0x04, 0x00-0x07: Hana ADAT
1334 * 0x06-0x07: Not used
1340 * 0x00, 0x00-0x1f: Silence
1341 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1344 * 0x08: Dock ADC 1 Left
1345 * 0x0c: Dock ADC 1 Right
1346 * 0x10: Dock ADC 2 Left
1348 * 0x14: Dock ADC 2 Right
1350 * 0x18-0x1f: Dock ADAT 0-7
1351 * 0x02, 0x00: Hamoa ADC Left
1352 * 0x02, 0x01: Hamoa ADC Right
1353 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1354 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1355 * 0x04, 0x00-0x07: Hana3 ADAT
1358 * 0x06-0x07: Not used
1362 * 0x00, 0x00-0x1f: Silence
1364 * 0x02, 0x00: ADC Left
1365 * 0x02, 0x01: ADC Right
1366 * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output
1367 * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output
1371 * 0x06-0x07: Not used
1374 * 0x00, 0x00-0x1f: Silence
1375 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1378 * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output
1379 * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output
1380 * 0x04-0x07: Not used
1383 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1384 * destinations using a mixer control for each destination - see emumixer.c.
1385 * Sources are either physical inputs of Hana, or inputs from Alice2/Tina -
1421 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1422 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1423 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1424 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1425 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1426 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1427 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1428 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1453 /* ------------------- CONSTANTS -------------------- */
1462 /* ------------------- STRUCTURES -------------------- */
1549 …efine snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (P…
1578 unsigned int channels; /* 16-bit channels count */
1633 // Chip-o-logy:
1634 // - All SB Live! cards use EMU10K1 chips
1635 // - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver
1636 // - Original Audigy uses CA0100 "Alice"
1637 // - Audigy 2 uses CA0102/CA10200 "Alice2"
1638 // - Has an interface for CA0151 (P16V) "Alice3"
1639 // - Audigy 2 Value uses CA0108/CA10300 "Tina"
1640 // - Approximately a CA0102 with an on-chip CA0151 (P17V)
1641 // - Audigy 2 ZS NB uses CA0109 "Tina2"
1642 // - Cardbus version of CA0108
1660 unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1665 unsigned int i2c_adc:1; /* I2C interface for ADC; requires ca0108_chip */
1666 unsigned int adc_1361t:1; /* Use Philips 1361T ADC */
1670 const char *id; /* for backward compatibility - can be NULL if not needed */
1743 spinlock_t reg_lock; // high-level driver lock
1744 spinlock_t emu_lock; // low-level i/o lock
1859 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >>… in snd_emu10k1_wc()