Lines Matching full:pdif
229 /* I2S0 can phase track the last S/PDIF input */
728 #define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
837 #define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */
838 #define A_SPRA 0x6b /* S/PDIF Host Record Address */
839 #define A_SPRC 0x6c /* S/PDIF Host Record Control */
962 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
963 // to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels
1155 * 0x1a: S/PDIF Left
1157 * 0x1e: S/PDIF Right
1158 * 0x02, 0x00: Hana S/PDIF Left
1159 * 0x02, 0x01: Hana S/PDIF Right
1181 * 0x12: Dock S/PDIF Left
1183 * 0x16: Dock S/PDIF Right
1185 * 0x02, 0x00: Hana3 S/PDIF Left
1186 * 0x02, 0x01: Hana3 S/PDIF Right
1197 * 0x02, 0x00: S/PDIF Left
1198 * 0x02, 0x01: S/PDIF Right
1304 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1305 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1306 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1307 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1308 #define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */
1332 * 0x05, 0x00: Hana S/PDIF Left
1333 * 0x05, 0x01: Hana S/PDIF Right
1347 * 0x12: Dock S/PDIF Left
1349 * 0x16: Dock S/PDIF Right
1356 * 0x05, 0x00: Hana3 S/PDIF Left
1357 * 0x05, 0x01: Hana3 S/PDIF Right
1369 * 0x05, 0x00: S/PDIF Left
1370 * 0x05, 0x01: S/PDIF Right
1444 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */
1445 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */
1446 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */
1447 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */
1722 unsigned int spdif_bits[3]; /* s/pdif out setup */