Lines Matching +full:18 +full:- +full:23
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
109 #define HSIO_PLL5G_CFG1_ENA_DIRECT BIT(18)
131 #define HSIO_PLL5G_CFG2_AMPC_SEL(x) (((x) << 16) & GENMASK(23, 16))
132 #define HSIO_PLL5G_CFG2_AMPC_SEL_M GENMASK(23, 16)
133 #define HSIO_PLL5G_CFG2_AMPC_SEL_X(x) (((x) & GENMASK(23, 16)) >> 16)
149 #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL(x) (((x) << 22) & GENMASK(23, 22))
150 #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M GENMASK(23, 22)
151 #define HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X(x) (((x) & GENMASK(23, 22)) >> 22)
155 #define HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT BIT(18)
169 #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
170 #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M GENMASK(23, 16)
171 #define HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
175 #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL(x) (((x) << 16) & GENMASK(23, 16))
176 #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M GENMASK(23, 16)
177 #define HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X(x) (((x) & GENMASK(23, 16)) >> 16)
181 #define HSIO_PLL5G_CFG6_REFCLK_SEL_SRC BIT(23)
222 #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT(x) (((x) << 20) & GENMASK(23, 20))
223 #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M GENMASK(23, 20)
224 #define HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X(x) (((x) & GENMASK(23, 20)) >> 20)
313 #define HSIO_S1G_OB_CFG_OB_SLP(x) (((x) << 17) & GENMASK(18, 17))
314 #define HSIO_S1G_OB_CFG_OB_SLP_M GENMASK(18, 17)
315 #define HSIO_S1G_OB_CFG_OB_SLP_X(x) (((x) & GENMASK(18, 17)) >> 17)
344 #define HSIO_S1G_COMMON_CFG_ENA_LANE BIT(18)
375 #define HSIO_S1G_DFT_CFG0_INV_DIS BIT(23)
379 #define HSIO_S1G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
380 #define HSIO_S1G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
381 #define HSIO_S1G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
446 #define HSIO_S6G_DIG_CFG_GP(x) (((x) << 16) & GENMASK(18, 16))
447 #define HSIO_S6G_DIG_CFG_GP_M GENMASK(18, 16)
448 #define HSIO_S6G_DIG_CFG_GP_X(x) (((x) & GENMASK(18, 16)) >> 16)
458 #define HSIO_S6G_DFT_CFG0_INV_DIS BIT(23)
462 #define HSIO_S6G_DFT_CFG0_TEST_MODE(x) (((x) << 16) & GENMASK(18, 16))
463 #define HSIO_S6G_DFT_CFG0_TEST_MODE_M GENMASK(18, 16)
464 #define HSIO_S6G_DFT_CFG0_TEST_MODE_X(x) (((x) & GENMASK(18, 16)) >> 16)
519 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
520 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M GENMASK(28, 23)
521 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
522 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1(x) (((x) << 18) & GENMASK(22, 18))
523 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M GENMASK(22, 18)
524 #define HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X(x) (((x) & GENMASK(22, 18)) >> 18)
570 #define HSIO_S6G_IB_CFG_IB_ICML_ADJ(x) (((x) << 20) & GENMASK(23, 20))
571 #define HSIO_S6G_IB_CFG_IB_ICML_ADJ_M GENMASK(23, 20)
572 #define HSIO_S6G_IB_CFG_IB_ICML_ADJ_X(x) (((x) & GENMASK(23, 20)) >> 20)
573 #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL(x) (((x) << 18) & GENMASK(19, 18))
574 #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M GENMASK(19, 18)
575 #define HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X(x) (((x) & GENMASK(19, 18)) >> 18)
626 #define HSIO_S6G_IB_CFG2_IB_OINFS(x) (((x) << 16) & GENMASK(18, 16))
627 #define HSIO_S6G_IB_CFG2_IB_OINFS_M GENMASK(18, 16)
628 #define HSIO_S6G_IB_CFG2_IB_OINFS_X(x) (((x) & GENMASK(18, 16)) >> 16)
641 #define HSIO_S6G_IB_CFG3_IB_INI_HP(x) (((x) << 18) & GENMASK(23, 18))
642 #define HSIO_S6G_IB_CFG3_IB_INI_HP_M GENMASK(23, 18)
643 #define HSIO_S6G_IB_CFG3_IB_INI_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
653 #define HSIO_S6G_IB_CFG4_IB_MAX_HP(x) (((x) << 18) & GENMASK(23, 18))
654 #define HSIO_S6G_IB_CFG4_IB_MAX_HP_M GENMASK(23, 18)
655 #define HSIO_S6G_IB_CFG4_IB_MAX_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
665 #define HSIO_S6G_IB_CFG5_IB_MIN_HP(x) (((x) << 18) & GENMASK(23, 18))
666 #define HSIO_S6G_IB_CFG5_IB_MIN_HP_M GENMASK(23, 18)
667 #define HSIO_S6G_IB_CFG5_IB_MIN_HP_X(x) (((x) & GENMASK(23, 18)) >> 18)
680 #define HSIO_S6G_OB_CFG_OB_POST0(x) (((x) << 23) & GENMASK(28, 23))
681 #define HSIO_S6G_OB_CFG_OB_POST0_M GENMASK(28, 23)
682 #define HSIO_S6G_OB_CFG_OB_POST0_X(x) (((x) & GENMASK(28, 23)) >> 23)
683 #define HSIO_S6G_OB_CFG_OB_PREC(x) (((x) << 18) & GENMASK(22, 18))
684 #define HSIO_S6G_OB_CFG_OB_PREC_M GENMASK(22, 18)
685 #define HSIO_S6G_OB_CFG_OB_PREC_X(x) (((x) & GENMASK(22, 18)) >> 18)
774 #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT(x) (((x) << 18) & GENMASK(23, 18))
775 #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M GENMASK(23, 18)
776 #define HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X(x) (((x) & GENMASK(23, 18)) >> 18)