fsl/qe/immap_qe.h

55 struct cp_qe {  struct
56 	__be32	cecr;		/* QE command register */
57 	__be32	ceccr;		/* QE controller configuration register */
58 	__be32	cecdr;		/* QE command data register */
59 	u8	res0[0xA];
60 	__be16	ceter;		/* QE timer event register */
61 	u8	res1[0x2];
62 	__be16	cetmr;		/* QE timers mask register */
63 	__be32	cetscr;		/* QE time-stamp timer control register */
64 	__be32	cetsr1;		/* QE time-stamp register 1 */
65 	__be32	cetsr2;		/* QE time-stamp register 2 */
66 	u8	res2[0x8];
67 	__be32	cevter;		/* QE virtual tasks event register */
68 	__be32	cevtmr;		/* QE virtual tasks mask register */
69 	__be16	cercr;		/* QE RAM control register */
70 	u8	res3[0x2];
71 	u8	res4[0x24];
72 	__be16	ceexe1;		/* QE external request 1 event register */
73 	u8	res5[0x2];
74 	__be16	ceexm1;		/* QE external request 1 mask register */
75 	u8	res6[0x2];
76 	__be16	ceexe2;		/* QE external request 2 event register */
77 	u8	res7[0x2];
78 	__be16	ceexm2;		/* QE external request 2 mask register */
79 	u8	res8[0x2];
80 	__be16	ceexe3;		/* QE external request 3 event register */
81 	u8	res9[0x2];
82 	__be16	ceexm3;		/* QE external request 3 mask register */
83 	u8	res10[0x2];
84 	__be16	ceexe4;		/* QE external request 4 event register */
85 	u8	res11[0x2];
86 	__be16	ceexm4;		/* QE external request 4 mask register */
87 	u8	res12[0x3A];
88 	__be32	ceurnr;		/* QE microcode revision number register */
89 	u8	res13[0x244];