Lines Matching +full:0 +full:x0400
54 u8 res6[0x22];
61 #define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
62 #define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
63 #define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
64 #define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
66 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
67 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
68 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
69 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
71 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
75 #define CPM_CR_INIT_TRX ((ushort)0x0000)
76 #define CPM_CR_INIT_RX ((ushort)0x0001)
77 #define CPM_CR_INIT_TX ((ushort)0x0002)
78 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
79 #define CPM_CR_STOP_TX ((ushort)0x0004)
80 #define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
81 #define CPM_CR_RESTART_TX ((ushort)0x0006)
82 #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
83 #define CPM_CR_SET_GADDR ((ushort)0x0008)
84 #define CPM_CR_SET_TIMER ((ushort)0x0008)
85 #define CPM_CR_STOP_IDMA ((ushort)0x000b)
97 #define BD_SC_EMPTY (0x8000) /* Receive is empty */
98 #define BD_SC_READY (0x8000) /* Transmit is ready */
99 #define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
100 #define BD_SC_INTRPT (0x1000) /* Interrupt on change */
101 #define BD_SC_LAST (0x0800) /* Last buffer in frame */
102 #define BD_SC_TC (0x0400) /* Transmit CRC */
103 #define BD_SC_CM (0x0200) /* Continuous mode */
104 #define BD_SC_ID (0x0100) /* Rec'd too many idles */
105 #define BD_SC_P (0x0100) /* xmt preamble */
106 #define BD_SC_BR (0x0020) /* Break received */
107 #define BD_SC_FR (0x0010) /* Framing error */
108 #define BD_SC_PR (0x0008) /* Parity error */
109 #define BD_SC_NAK (0x0004) /* NAK - did not respond */
110 #define BD_SC_OV (0x0002) /* Overrun */
111 #define BD_SC_UN (0x0002) /* Underrun */
112 #define BD_SC_CD (0x0001) /* */
113 #define BD_SC_CL (0x0001) /* Collision */
118 #define BD_ENET_RX_EMPTY (0x8000)
119 #define BD_ENET_RX_WRAP (0x2000)
120 #define BD_ENET_RX_INTR (0x1000)
121 #define BD_ENET_RX_LAST (0x0800)
122 #define BD_ENET_RX_FIRST (0x0400)
123 #define BD_ENET_RX_MISS (0x0100)
124 #define BD_ENET_RX_BC (0x0080) /* FCC Only */
125 #define BD_ENET_RX_MC (0x0040) /* FCC Only */
126 #define BD_ENET_RX_LG (0x0020)
127 #define BD_ENET_RX_NO (0x0010)
128 #define BD_ENET_RX_SH (0x0008)
129 #define BD_ENET_RX_CR (0x0004)
130 #define BD_ENET_RX_OV (0x0002)
131 #define BD_ENET_RX_CL (0x0001)
132 #define BD_ENET_RX_STATS (0x01ff) /* All status bits */
137 #define BD_ENET_TX_READY (0x8000)
138 #define BD_ENET_TX_PAD (0x4000)
139 #define BD_ENET_TX_WRAP (0x2000)
140 #define BD_ENET_TX_INTR (0x1000)
141 #define BD_ENET_TX_LAST (0x0800)
142 #define BD_ENET_TX_TC (0x0400)
143 #define BD_ENET_TX_DEF (0x0200)
144 #define BD_ENET_TX_HB (0x0100)
145 #define BD_ENET_TX_LC (0x0080)
146 #define BD_ENET_TX_RL (0x0040)
147 #define BD_ENET_TX_RCMASK (0x003c)
148 #define BD_ENET_TX_UN (0x0002)
149 #define BD_ENET_TX_CSL (0x0001)
150 #define BD_ENET_TX_STATS (0x03ff) /* All status bits */
154 #define BD_SCC_TX_LAST (0x0800)
158 #define BD_I2C_START (0x0400)