soc/canaan/k210-sysctl.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
10  * Kendryte K210 SoC system controller registers offsets.
11  * Taken from Kendryte SDK (kendryte-standalone-sdk).
15 #define K210_SYSCTL_PLL0	0x08 /* PLL0 controller */
16 #define K210_SYSCTL_PLL1	0x0C /* PLL1 controller */
17 #define K210_SYSCTL_PLL2	0x10 /* PLL2 controller */
20 #define K210_SYSCTL_SEL0	0x20 /* Clock select controller 0 */
21 #define K210_SYSCTL_SEL1	0x24 /* Clock select controller 1 */
23 #define K210_SYSCTL_EN_PERI	0x2C /* Peripheral clock enable */
25 #define K210_SYSCTL_PERI_RESET	0x34 /* Peripheral reset controller */
26 #define K210_SYSCTL_THR0	0x38 /* Clock threshold controller 0 */
27 #define K210_SYSCTL_THR1	0x3C /* Clock threshold controller 1 */
28 #define K210_SYSCTL_THR2	0x40 /* Clock threshold controller 2 */
29 #define K210_SYSCTL_THR3	0x44 /* Clock threshold controller 3 */
30 #define K210_SYSCTL_THR4	0x48 /* Clock threshold controller 4 */
31 #define K210_SYSCTL_THR5	0x4C /* Clock threshold controller 5 */
32 #define K210_SYSCTL_THR6	0x50 /* Clock threshold controller 6 */
33 #define K210_SYSCTL_MISC	0x54 /* Miscellaneous controller */
34 #define K210_SYSCTL_PERI	0x58 /* Peripheral controller */
35 #define K210_SYSCTL_SPI_SLEEP	0x5C /* SPI sleep controller */
39 #define K210_SYSCTL_POWER_SEL	0x6C /* IO Power Mode Select controller */