1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * This driver supports the following PXA CPU/SSP ports:-
49 #define SSCR0_DSS	GENMASK(3, 0)	/* Data Size Select (mask) */
50 #define SSCR0_DataSize(x)  ((x) - 1)	/* Data Size Select [4..16] */  argument
51 #define SSCR0_FRF	GENMASK(5, 4)	/* FRame Format (mask) */
57 #define SSCR0_SCR(x)	((x) << 8)	/* Serial Clock Rate (mask) */  argument
62 #define SSCR0_RIM	BIT(22)		/* Receive FIFO overrun interrupt mask */
63 #define SSCR0_TUM	BIT(23)		/* Transmit FIFO underrun interrupt mask */
64 #define SSCR0_FRDC	GENMASK(26, 24)	/* Frame rate divider control (mask) */
65 #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)	/* Time slots per frame [1..8] */  argument
72 #define SSCR1_LBM	BIT(2)		/* Loop-Back Mode */
88 #define SSSR_TFL_MASK	GENMASK(11, 8)	/* Transmit FIFO Level mask */
89 #define SSSR_RFL_MASK	GENMASK(15, 12)	/* Receive FIFO Level mask */
91 #define SSCR1_TFT	GENMASK(9, 6)	/* Transmit FIFO Threshold (mask) */
92 #define SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..16] */  argument
93 #define SSCR1_RFT	GENMASK(13, 10)	/* Receive FIFO Threshold (mask) */
94 #define SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..16] */  argument
99 #define CE4100_SSSR_TFL_MASK	GENMASK(9, 8)	/* Transmit FIFO Level mask */
100 #define CE4100_SSSR_RFL_MASK	GENMASK(13, 12)	/* Receive FIFO Level mask */
102 #define CE4100_SSCR1_TFT	GENMASK(7, 6)	/* Transmit FIFO Threshold (mask) */
103 #define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..4] */  argument
104 #define CE4100_SSCR1_RFT	GENMASK(11, 10)	/* Receive FIFO Threshold (mask) */
105 #define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10)	/* level [1..4] */  argument
111 #define QUARK_X1000_SSCR0_DSS		GENMASK(4, 0)	/* Data Size Select (mask) */
112 #define QUARK_X1000_SSCR0_DataSize(x)	((x) - 1)	/* Data Size Select [4..32] */  argument
113 #define QUARK_X1000_SSCR0_FRF		GENMASK(6, 5)	/* FRame Format (mask) */
119 #define QUARK_X1000_SSSR_TFL_MASK	GENMASK(12, 8)	/* Transmit FIFO Level mask */
120 #define QUARK_X1000_SSSR_RFL_MASK	GENMASK(17, 13)	/* Receive FIFO Level mask */
122 #define QUARK_X1000_SSCR1_TFT	GENMASK(10, 6)	/* Transmit FIFO Threshold (mask) */
123 #define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6)	/* level [1..32] */  argument
124 #define QUARK_X1000_SSCR1_RFT	GENMASK(15, 11)	/* Receive FIFO Threshold (mask) */
125 #define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11)	/* level [1..32] */  argument
131 #define SSCR0_PSP		(3 << 4)	/* PSP - Programmable Serial Protocol */
137 #define SSCR1_TINTE		BIT(19)		/* Receiver Time-out Interrupt enable */
152 #define SSSR_TINT		BIT(19)		/* Receiver Time-out Interrupt */
158 #define SSPSP_SCMODE(x)		((x) << 0)	/* Serial Bit Rate Clock Mode */  argument
161 #define SSPSP_STRTDLY(x)	((x) << 4)	/* Start Delay */  argument
162 #define SSPSP_DMYSTRT(x)	((x) << 7)	/* Dummy Start */  argument
163 #define SSPSP_SFRMDLY(x)	((x) << 9)	/* Serial Frame Delay */  argument
164 #define SSPSP_SFRMWDTH(x)	((x) << 16)	/* Serial Frame Width */  argument
165 #define SSPSP_DMYSTOP(x)	((x) << 23)	/* Dummy Stop */  argument
169 #define SSPSP_EDMYSTRT(x)	((x) << 26)     /* Extended Dummy Start */  argument
170 #define SSPSP_EDMYSTOP(x)	((x) << 28)     /* Extended Dummy Stop */  argument
173 #define SSACD_ACDS(x)		((x) << 0)	/* Audio clock divider select */  argument
183 #define SSACD_ACPS(x)		((x) << 4)	/* Audio clock PLL select */  argument
193 #define SFIFOL_TFL_MASK		GENMASK(15, 0)	/* Transmit FIFO Level mask */
194 #define SFIFOL_RFL_MASK		GENMASK(31, 16)	/* Receive FIFO Level mask */
196 #define SFIFOTT_TFT		GENMASK(15, 0)	/* Transmit FIFO Threshold (mask) */
197 #define SFIFOTT_TxThresh(x)	(((x) - 1) << 0)	/* TX FIFO trigger threshold / level */  argument
198 #define SFIFOTT_RFT		GENMASK(31, 16)	/* Receive FIFO Threshold (mask) */
199 #define SFIFOTT_RxThresh(x)	(((x) - 1) << 16)	/* RX FIFO trigger threshold / level */  argument
203 #define SSITF_TxHiThresh(x)	(((x) - 1) << 0)  argument
204 #define SSITF_TxLoThresh(x)	(((x) - 1) << 8)  argument
207 #define SSIRF_RxThresh(x)	((x) - 1)  argument
215 	PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
216 	PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
253  * pxa_ssp_write_reg - Write to a SSP register
261 	__raw_writel(val, dev->mmio_base + reg);  in pxa_ssp_write_reg()
265  * pxa_ssp_read_reg - Read from a SSP register
272 	return __raw_readl(dev->mmio_base + reg);  in pxa_ssp_read_reg()