1201 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1229 	/* NUM OF CAP Types */
1260 #define MLX5_CAP_GEN(mdev, cap) \  argument
1261 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1263 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1264 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1266 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1267 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1269 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1270 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1272 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1273 	MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1275 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1276 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1278 #define MLX5_CAP_ETH(mdev, cap) \  argument
1280 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1282 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1284 		 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1286 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1287 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1289 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1290 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1292 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1293 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1295 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1296 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1298 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1299 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1301 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1302 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1304 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1305 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1307 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1308 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1310 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1311 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1313 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1314 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1316 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1317 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1319 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1320 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1322 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1324 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1326 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1327 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1329 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1330 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1332 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1333 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1335 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \  argument
1336 	MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1338 #define MLX5_CAP_ESW(mdev, cap) \  argument
1340 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1342 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1344 		(mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1346 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \  argument
1348 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1350 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \  argument
1352 		 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1354 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \  argument
1356 		 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1358 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \  argument
1359 	MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1361 #define MLX5_CAP_ODP(mdev, cap)\  argument
1362 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1364 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1365 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1367 #define MLX5_CAP_QOS(mdev, cap)\  argument
1368 	MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1370 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1371 	MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1396 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1397 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1399 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1400 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1402 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1403 	MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1405 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1406 	MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1408 #define MLX5_CAP_TLS(mdev, cap) \  argument
1409 	MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1411 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1412 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1414 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1416 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1418 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1420 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1422 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1423 	MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1425 #define MLX5_CAP_CRYPTO(mdev, cap)\  argument
1426 	MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1428 #define MLX5_CAP_MACSEC(mdev, cap)\  argument
1429 	MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)