dt-bindings/memory/tegra234-mc.h

1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
180 /* MSS internal memqual MIU7 read clients */
182 /* MSS internal memqual MIU7 write clients */
184 /* MSS internal memqual MIU8 read clients */
186 /* MSS internal memqual MIU8 write clients */
188 /* MSS internal memqual MIU9 read clients */
190 /* MSS internal memqual MIU9 write clients */
192 /* MSS internal memqual MIU10 read clients */
194 /* MSS internal memqual MIU10 write clients */
196 /* MSS internal memqual MIU11 read clients */
198 /* MSS internal memqual MIU11 write clients */
200 /* MSS internal memqual MIU12 read clients */
202 /* MSS internal memqual MIU12 write clients */
204 /* MSS internal memqual MIU13 read clients */
206 /* MSS internal memqual MIU13 write clients */
210 /* High-definition audio (HDA) read clients */
212 /* Host channel data read clients */
228 /* PCIE6 read clients */
230 /* PCIE6 write clients */
232 /* PCIE7 read clients */
235 /* DLA0ARDB read clients */
237 /* DLA0ARDB1 read clients */
241 /* DLA1ARDB read clients */
243 /* PCIE7 write clients */
245 /* PCIE8 read clients */
247 /* High-definition audio (HDA) write clients */
249 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
253 /* PCIE8 write clients */
255 /* PCIE9 read clients */
257 /* PCIE6r1 read clients */
259 /* PCIE9 write clients */
261 /* PCIE10 read clients */
263 /* PCIE10 write clients */
265 /* ISP read client for Crossbar A */
267 /* ISP read client 1 for Crossbar A */
269 /* ISP Write client for Crossbar A */
271 /* ISP Write client Crossbar B */
273 /* PCIE10r1 read clients */
275 /* PCIE7r1 read clients */
277 /* XUSB_HOST read clients */
279 /* XUSB_HOST write clients */
281 /* XUSB read clients */
283 /* XUSB_DEV write clients */
287 /* TSEC Memory Write Client Description */
291 /* MGBE0 read client */
293 /* MGBEB read client */
295 /* MGBEC read client */
297 /* MGBED read client */
299 /* MGBE0 write client */
305 /* MGBEB write client */
307 /* sdmmca memory read client */
309 /* MGBEC write client */
311 /* sdmmcd memory read client */
313 /* sdmmca memory write client */
315 /* MGBED write client */
317 /* sdmmcd memory write client */
321 /* SE Memory Write Client Description */
325 /* DLA1ARDB1 read clients */
329 /* VI FLACON read clients */
331 /* VI Write client */
333 /* VI Write client */
335 /* NISO display read client */
347 /* Audio Processing (APE) engine read clients */
349 /* Audio Processing (APE) engine write clients */
357 /* SE Memory Write Client Description */
359 /* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */
361 /* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */
363 /* ETR read clients */
365 /* ETR write clients */
367 /* AXI Switch read client */
369 /* AXI Switch write client */
371 /* EQOS read client */
373 /* EQOS write client */
375 /* UFSHC read client */
377 /* UFSHC write client */
379 /* NVDISPLAY read client */
381 /* BPMP read client */
383 /* BPMP write client */
385 /* BPMPDMA read client */
387 /* BPMPDMA write client */
389 /* AON read client */
391 /* AON write client */
393 /* AONDMA read client */
395 /* AONDMA write client */
397 /* SCE read client */
399 /* SCE write client */
401 /* SCEDMA read client */
403 /* SCEDMA write client */
405 /* APEDMA read client */
407 /* APEDMA write client */
409 /* NVDISPLAY read client instance 2 */
412 /* MSS internal memqual MIU0 read clients */
414 /* MSS internal memqual MIU0 write clients */
416 /* MSS internal memqual MIU1 read clients */
418 /* MSS internal memqual MIU1 write clients */
420 /* MSS internal memqual MIU2 read clients */
422 /* MSS internal memqual MIU2 write clients */
424 /* MSS internal memqual MIU3 read clients */
426 /* MSS internal memqual MIU3 write clients */
428 /* MSS internal memqual MIU4 read clients */
430 /* MSS internal memqual MIU4 write clients */
440 /* VI FLACON read clients */
442 /* VIFAL write clients */
444 /* DLA0ARDA read clients */
446 /* DLA0 Falcon read clients */
448 /* DLA0 write clients */
450 /* DLA0 write clients */
452 /* DLA1ARDA read clients */
454 /* DLA1 Falcon read clients */
456 /* DLA1 write clients */
458 /* DLA1 write clients */
460 /* PVA0RDA read clients */
462 /* PVA0RDB read clients */
464 /* PVA0RDC read clients */
466 /* PVA0WRA write clients */
468 /* PVA0WRB write clients */
470 /* PVA0WRC write clients */
472 /* RCE read client */
474 /* RCE write client */
476 /* RCEDMA read client */
478 /* RCEDMA write client */
480 /* PCIE0 read clients */
482 /* PCIE0 write clients */
484 /* PCIE1 read clients */
486 /* PCIE1 write clients */
488 /* PCIE2 read clients */
490 /* PCIE2 write clients */
492 /* PCIE3 read clients */
494 /* PCIE3 write clients */
496 /* PCIE4 read clients */
498 /* PCIE4 write clients */
500 /* PCIE5 read clients */
502 /* PCIE5 write clients */
504 /* ISP read client 1 for Crossbar A */
510 /* DLA0ARDA1 read clients */
512 /* DLA1ARDA1 read clients */
514 /* PVA0RDA1 read clients */
516 /* PVA0RDB1 read clients */
518 /* PCIE5r1 read clients */
521 /* ISP read client for Crossbar A */
528 /* MSS internal memqual MIU5 read clients */
530 /* MSS internal memqual MIU5 write clients */
532 /* MSS internal memqual MIU6 read clients */
534 /* MSS internal memqual MIU6 write clients */