dt-bindings/memory/tegra194-mc.h

147 /* MSS internal memqual MIU7 read clients */
149 /* MSS internal memqual MIU7 write clients */
151 /* High-definition audio (HDA) read clients */
153 /* Host channel data read clients */
156 /* SATA read clients */
158 /* Reads from Cortex-A9 4 CPU cores via the L2 cache */
161 /* High-definition audio (HDA) write clients */
163 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
165 /* SATA write clients */
167 /* ISP read client for Crossbar A */
169 /* ISP read client 1 for Crossbar A */
171 /* ISP Write client for Crossbar A */
173 /* ISP Write client Crossbar B */
175 /* XUSB_HOST read clients */
177 /* XUSB_HOST write clients */
179 /* XUSB read clients */
181 /* XUSB_DEV write clients */
183 /* sdmmca memory read client */
185 /* sdmmc memory read client */
187 /* sdmmcd memory read client */
189 /* sdmmca memory write client */
191 /* sdmmc memory write client */
193 /* sdmmcd memory write client */
197 /* VI Write client */
201 /* Audio Processing (APE) engine read clients */
203 /* Audio Processing (APE) engine write clients */
207 /* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */
209 /* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */
211 /* ETR read clients */
213 /* ETR write clients */
215 /* AXI Switch read client */
217 /* AXI Switch write client */
219 /* EQOS read client */
221 /* EQOS write client */
223 /* UFSHC read client */
225 /* UFSHC write client */
227 /* NVDISPLAY read client */
229 /* BPMP read client */
231 /* BPMP write client */
233 /* BPMPDMA read client */
235 /* BPMPDMA write client */
237 /* AON read client */
239 /* AON write client */
241 /* AONDMA read client */
243 /* AONDMA write client */
245 /* SCE read client */
247 /* SCE write client */
249 /* SCEDMA read client */
251 /* SCEDMA write client */
253 /* APEDMA read client */
255 /* APEDMA write client */
257 /* NVDISPLAY read client instance 2 */
261 /* MSS internal memqual MIU0 read clients */
263 /* MSS internal memqual MIU0 write clients */
265 /* MSS internal memqual MIU1 read clients */
267 /* MSS internal memqual MIU1 write clients */
269 /* MSS internal memqual MIU2 read clients */
271 /* MSS internal memqual MIU2 write clients */
273 /* MSS internal memqual MIU3 read clients */
275 /* MSS internal memqual MIU3 write clients */
277 /* MSS internal memqual MIU4 read clients */
279 /* MSS internal memqual MIU4 write clients */
289 /* VI FLACON read clients */
291 /* VIFAL write clients */
293 /* DLA0ARDA read clients */
295 /* DLA0 Falcon read clients */
297 /* DLA0 write clients */
299 /* DLA0 write clients */
301 /* DLA1ARDA read clients */
303 /* DLA1 Falcon read clients */
305 /* DLA1 write clients */
307 /* DLA1 write clients */
309 /* PVA0RDA read clients */
311 /* PVA0RDB read clients */
313 /* PVA0RDC read clients */
315 /* PVA0WRA write clients */
317 /* PVA0WRB write clients */
319 /* PVA0WRC write clients */
321 /* PVA1RDA read clients */
323 /* PVA1RDB read clients */
325 /* PVA1RDC read clients */
327 /* PVA1WRA write clients */
329 /* PVA1WRB write clients */
331 /* PVA1WRC write clients */
333 /* RCE read client */
335 /* RCE write client */
337 /* RCEDMA read client */
339 /* RCEDMA write client */
343 /* PCIE0 read clients */
345 /* PCIE0 write clients */
347 /* PCIE1 read clients */
349 /* PCIE1 write clients */
351 /* PCIE2 read clients */
353 /* PCIE2 write clients */
355 /* PCIE3 read clients */
357 /* PCIE3 write clients */
359 /* PCIE4 read clients */
361 /* PCIE4 write clients */
363 /* PCIE5 read clients */
365 /* PCIE5 write clients */
367 /* ISP read client 1 for Crossbar A */
373 /* DLA0ARDA1 read clients */
375 /* DLA1ARDA1 read clients */
377 /* PVA0RDA1 read clients */
379 /* PVA0RDB1 read clients */
381 /* PVA1RDA1 read clients */
383 /* PVA1RDB1 read clients */
385 /* PCIE5r1 read clients */
389 /* ISP read client for Crossbar A */
391 /* PCIE0 read clients */
401 /* MSS internal memqual MIU5 read clients */
403 /* MSS internal memqual MIU5 write clients */
405 /* MSS internal memqual MIU6 read clients */
407 /* MSS internal memqual MIU6 write clients */