dt-bindings/memory/mt8186-memory-port.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
15  * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18  * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22  * modules    dma-address-region	larbs-ports
25  * cam/mdp     8G ~ 12G                 the other larbs.
26  * N/A         12G ~ 16G
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
52 /* LARB 4 -- VDEC */
65 #define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT	MTK_M4U_ID(4, 12)
68 /* LARB 7 -- VENC */
81 #define IOMMU_PORT_L7_JPGENC_BSDMA	MTK_M4U_ID(7, 12)
83 /* LARB 8 -- WPE */
88 /* LARB 9 -- IMG-1 */
101 #define IOMMU_PORT_L9_IMG_TIMGO_D1	MTK_M4U_ID(9, 12)
106 #define IOMMU_PORT_L9_IMG_WPE_WDMA	MTK_M4U_ID(9, 17)
119 /* LARB 11 -- IMG-2 */
132 #define IOMMU_PORT_L11_IMG_TIMGO_D1	MTK_M4U_ID(11, 12)
137 #define IOMMU_PORT_L11_IMG_WPE_WDMA	MTK_M4U_ID(11, 17)
150 /* LARB 13 -- CAM */
161 /* LARB 14 -- CAM */
165 /* LARB 16 -- RAW-A */
178 #define IOMMU_PORT_L16_CAM_CRZO_R1_A	MTK_M4U_ID(16, 12)
184 /* LARB 17 -- RAW-B */
185 #define IOMMU_PORT_L17_CAM_IMGO_R1_B	MTK_M4U_ID(17, 0)
186 #define IOMMU_PORT_L17_CAM_RRZO_R1_B	MTK_M4U_ID(17, 1)
187 #define IOMMU_PORT_L17_CAM_CQI_R1_B	MTK_M4U_ID(17, 2)
188 #define IOMMU_PORT_L17_CAM_BPCI_R1_B	MTK_M4U_ID(17, 3)
189 #define IOMMU_PORT_L17_CAM_YUVO_R1_B	MTK_M4U_ID(17, 4)
190 #define IOMMU_PORT_L17_CAM_UFDI_R2_B	MTK_M4U_ID(17, 5)
191 #define IOMMU_PORT_L17_CAM_RAWI_R2_B	MTK_M4U_ID(17, 6)
192 #define IOMMU_PORT_L17_CAM_RAWI_R3_B	MTK_M4U_ID(17, 7)
193 #define IOMMU_PORT_L17_CAM_AAO_R1_B	MTK_M4U_ID(17, 8)
194 #define IOMMU_PORT_L17_CAM_AFO_R1_B	MTK_M4U_ID(17, 9)
195 #define IOMMU_PORT_L17_CAM_FLKO_R1_B	MTK_M4U_ID(17, 10)
196 #define IOMMU_PORT_L17_CAM_LCESO_R1_B	MTK_M4U_ID(17, 11)
197 #define IOMMU_PORT_L17_CAM_CRZO_R1_B	MTK_M4U_ID(17, 12)
198 #define IOMMU_PORT_L17_CAM_LTMSO_R1_B	MTK_M4U_ID(17, 13)
199 #define IOMMU_PORT_L17_CAM_RSSO_R1_B	MTK_M4U_ID(17, 14)
200 #define IOMMU_PORT_L17_CAM_AAHO_R1_B	MTK_M4U_ID(17, 15)
201 #define IOMMU_PORT_L17_CAM_LSCI_R1_B	MTK_M4U_ID(17, 16)
203 /* LARB 19 -- IPE */
209 /* LARB 20 -- IPE */