dt-bindings/clock/tegra234-clock.h

12 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */
14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
18 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
20 /** @brief output of gate CLK_ENB_APB2APE */
22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
32 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
34 /** @brief output of gate CLK_ENB_CAN2_HOST */
36 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
38 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
40 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
42 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
44 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
46 /** @brief output of gate CLK_ENB_DPAUX */
48 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */
51  * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY
56 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
60 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
62 /** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
64 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
68 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
70 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
85 /** @brief output of gate CLK_ENB_EQOS_RX */
87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
89 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
91 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
93 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
95 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
97 /** @brief output of gate CLK_ENB_FUSE */
99 /** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */
103 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
104 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
108 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
110 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
112 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
114 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
116 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
118 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
120 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
122 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
124 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
128 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
132 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
136 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
140 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
144 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
148 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
152 /** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */
154 /** @brief output of gate CLK_ENB_MIPI_CAL */
156 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
158 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
160 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
162 /** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */
164 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
166 /** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */
168 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
170 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
172 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
174 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
176 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
178 /** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */
180 /** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */
182 /** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */
184 /** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */
188 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
190 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
194 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */
202 /** @brief PLLP vco output */
204 /** @brief PLLP clk output */
208 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
210 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
212 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
214 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
216 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
218 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
220 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
222 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
224 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
226 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC output */
228 /** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */
230 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */
232 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
234 /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
236 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
240 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
242 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */
246 /** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */
250 /** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */
252 /** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */
254 /** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */
256 /** @brief output of gate CLK_ENB_SOR_SAFE */
258 /** @brief SOR_CLK_CTRL__0_DIV divider output */
260 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
262 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
264 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
266 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */
268 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
270 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
272 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
274 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
276 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
278 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
280 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
282 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
284 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
286 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
288 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
290 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
292 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
296 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */
298 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
300 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */
302 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
304 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
306 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
308 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
310 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
312 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
314 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */
316 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
318 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
320 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
322 /** @brief output of gate CLK_ENB_USB2_TRK */
324 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
326 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
328 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */
330 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */
332 /** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */
334 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */
336 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */
338 /** @brief output of gate CLK_ENB_PEX2_CORE_9 */
348 /** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */
350 /** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */
354 /** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */
356 /** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */
358 /** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */
360 /** @brief CLKOUT_AB output from DSI BRICK A (dsi_clkout_ab) */
362 /** @brief output of gate CLK_ENB_PEX2_CORE_10 */
364 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */
366 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */
368 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */
372 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output (qspi0_2x_pm_clk) */
374 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output (qspi1_2x_pm_clk) */
376 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 (qspi0_pm…
378 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 (qspi1_pm…
380 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */
410 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */
414 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */
416 /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */
420 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
422 /** @brief output of gate CLK_ENB_PEX0_CORE_0 */
424 /** @brief output of gate CLK_ENB_PEX0_CORE_1 */
426 /** @brief output of gate CLK_ENB_PEX0_CORE_2 */
428 /** @brief output of gate CLK_ENB_PEX0_CORE_3 */
430 /** @brief output of gate CLK_ENB_PEX0_CORE_4 */
432 /** @brief output of gate CLK_ENB_PEX1_CORE_5 */
448 /** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */
456 /** @brief output of the mux controlled by PLLC4_CLK_SEL */
478 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */
480 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */
482 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */
484 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */
486 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */
488 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */
490 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */
494 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output  */
500 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */
506 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */
512 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */
527 /** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */
531 /** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */
545 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */
547 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */
557 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
561 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */
565 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */
567 /** @brief output of gate CLK_ENB_BPMP_CPU */
569 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */
571 /** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */
573 /** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */
575 /** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */
577 /** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */
583 /** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */
591 /** @brief output of EMC CDB side A fixed (DIV4)  divider */
593 /** @brief output of EMC CDB side B fixed (DIV4)  divider */
595 /** @brief output of EMC CDB side C fixed (DIV4)  divider */
597 /** @brief output of EMC CDB side D fixed (DIV4)  divider */
601 /** @brief CLK_ENB_PLLREFE_OUT gate output */
605 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */
607 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */
613 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */
617 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */
619 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
621 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */
623 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */
625 /** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */
635 /** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
637 /** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */
639 /** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
641 /** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
647 /** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
649 /** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
651 /** @brief output of SW_MPHY_L0_RX_LS_BIT divider in  CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
665 /** @brief Monitored branch of MGBE0 RX PCS mux output */
667 /** @brief Monitored branch of MGBE1 RX PCS mux output */
669 /** @brief Monitored branch of MGBE2 RX PCS mux output */
671 /** @brief Monitored branch of MGBE3 RX PCS mux output */
673 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */
675 /** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */
689 /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
691 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
693 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
695 /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
697 /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
699 /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
701 /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
703 /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
705 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
707 /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
709 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
711 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
713 /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
715 /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
717 /** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */
719 /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
721 /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
723 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
725 /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
727 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
729 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
731 /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
733 /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
735 /** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */
737 /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
739 /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
741 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
743 /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
745 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
747 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
749 /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
751 /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
753 /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
755 /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
757 /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
759 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
761 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */
763 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */
765 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */
767 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */
769 /** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */
771 /** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */
773 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */
775 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */
777 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */
781 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */
783 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */
785 /** @brief Monitored output of I2S7 pad macro mux */
789 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */
791 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */
793 /** @brief Monitored output of I2S8 pad macro mux */
810 /** @brief output of gate CLK_ENB_SCE_CPU */
812 /** @brief output of gate CLK_ENB_RCE_CPU */
814 /** @brief output of gate CLK_ENB_DCE_CPU */
816 /** @brief DSIPLL VCO output */
818 /** @brief DSIPLL SYNC_CLKOUTP/N differential output */
820 /** @brief DSIPLL SYNC_CLKOUTA output */
822 /** @brief SPPLL0 VCO output */
824 /** @brief SPPLL0 SYNC_CLKOUTP/N differential output */
826 /** @brief SPPLL0 SYNC_CLKOUTA output */
828 /** @brief SPPLL0 SYNC_CLKOUTB output */
830 /** @brief SPPLL0 CLKOUT_DIVBY10 output */
832 /** @brief SPPLL0 CLKOUT_DIVBY25 output */
834 /** @brief SPPLL0 CLKOUT_DIVBY27P/N differential output */
836 /** @brief SPPLL1 VCO output */
838 /** @brief SPPLL1 SYNC_CLKOUTP/N differential output */
840 /** @brief SPPLL1 CLKOUT_DIVBY27P/N differential output */
854 /** @brief DISPPLL output */
856 /** @brief DISPHUBPLL output */
858 /** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */
860 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
864 /** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE_CLK_SRC switch output (dsi_core_clk) */
866 /** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */
868 /** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */
870 /** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */
872 /** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG__0 output */
888 /** @brief EMC PLLHUB output */
890 /** @brief output of fixed (DIV2) MC HUB divider */
892 /** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */
894 /** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */
896 /** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */
898 /** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */