dt-bindings/clock/r9a07g043-cpg.h

1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
32 #define R9A07G043_CA55_SCLK		0	/* RZ/G2UL Only */
33 #define R9A07G043_CA55_PCLK		1	/* RZ/G2UL Only */
34 #define R9A07G043_CA55_ATCLK		2	/* RZ/G2UL Only */
35 #define R9A07G043_CA55_GICCLK		3	/* RZ/G2UL Only */
36 #define R9A07G043_CA55_PERICLK		4	/* RZ/G2UL Only */
37 #define R9A07G043_CA55_ACLK		5	/* RZ/G2UL Only */
38 #define R9A07G043_CA55_TSCLK		6	/* RZ/G2UL Only */
39 #define R9A07G043_GIC600_GICCLK		7	/* RZ/G2UL Only */
40 #define R9A07G043_IA55_CLK		8	/* RZ/G2UL Only */
41 #define R9A07G043_IA55_PCLK		9	/* RZ/G2UL Only */
42 #define R9A07G043_MHU_PCLK		10	/* RZ/G2UL Only */
53 #define R9A07G043_WDT2_PCLK		21	/* RZ/G2UL Only */
54 #define R9A07G043_WDT2_CLK		22	/* RZ/G2UL Only */
65 #define R9A07G043_ISU_ACLK		33	/* RZ/G2UL Only */
66 #define R9A07G043_ISU_PCLK		34	/* RZ/G2UL Only */
67 #define R9A07G043_CRU_SYSCLK		35	/* RZ/G2UL Only */
68 #define R9A07G043_CRU_VCLK		36	/* RZ/G2UL Only */
69 #define R9A07G043_CRU_PCLK		37	/* RZ/G2UL Only */
70 #define R9A07G043_CRU_ACLK		38	/* RZ/G2UL Only */
71 #define R9A07G043_LCDC_CLK_A		39	/* RZ/G2UL Only */
72 #define R9A07G043_LCDC_CLK_P		40	/* RZ/G2UL Only */
73 #define R9A07G043_LCDC_CLK_D		41	/* RZ/G2UL Only */
82 #define R9A07G043_SRC_CLKP		50	/* RZ/G2UL Only */
111 #define R9A07G043_NCEPLDM_DM_CLK	79	/* RZ/Five Only */
112 #define R9A07G043_NCEPLDM_ACLK		80	/* RZ/Five Only */
113 #define R9A07G043_NCEPLDM_TCK		81	/* RZ/Five Only */
114 #define R9A07G043_NCEPLMT_ACLK		82	/* RZ/Five Only */
115 #define R9A07G043_NCEPLIC_ACLK		83	/* RZ/Five Only */
116 #define R9A07G043_AX45MP_CORE0_CLK	84	/* RZ/Five Only */
117 #define R9A07G043_AX45MP_ACLK		85	/* RZ/Five Only */
118 #define R9A07G043_IAX45_CLK		86	/* RZ/Five Only */
119 #define R9A07G043_IAX45_PCLK		87	/* RZ/Five Only */
122 #define R9A07G043_CA55_RST_1_0		0	/* RZ/G2UL Only */
123 #define R9A07G043_CA55_RST_1_1		1	/* RZ/G2UL Only */
124 #define R9A07G043_CA55_RST_3_0		2	/* RZ/G2UL Only */
125 #define R9A07G043_CA55_RST_3_1		3	/* RZ/G2UL Only */
126 #define R9A07G043_CA55_RST_4		4	/* RZ/G2UL Only */
127 #define R9A07G043_CA55_RST_5		5	/* RZ/G2UL Only */
128 #define R9A07G043_CA55_RST_6		6	/* RZ/G2UL Only */
129 #define R9A07G043_CA55_RST_7		7	/* RZ/G2UL Only */
130 #define R9A07G043_CA55_RST_8		8	/* RZ/G2UL Only */
131 #define R9A07G043_CA55_RST_9		9	/* RZ/G2UL Only */
132 #define R9A07G043_CA55_RST_10		10	/* RZ/G2UL Only */
133 #define R9A07G043_CA55_RST_11		11	/* RZ/G2UL Only */
134 #define R9A07G043_CA55_RST_12		12	/* RZ/G2UL Only */
135 #define R9A07G043_GIC600_GICRESET_N	13	/* RZ/G2UL Only */
136 #define R9A07G043_GIC600_DBG_GICRESET_N	14	/* RZ/G2UL Only */
137 #define R9A07G043_IA55_RESETN		15	/* RZ/G2UL Only */
138 #define R9A07G043_MHU_RESETN		16	/* RZ/G2UL Only */
148 #define R9A07G043_WDT2_PRESETN		26	/* RZ/G2UL Only */
152 #define R9A07G043_ISU_ARESETN		30	/* RZ/G2UL Only */
153 #define R9A07G043_ISU_PRESETN		31	/* RZ/G2UL Only */
154 #define R9A07G043_CRU_CMN_RSTB		32	/* RZ/G2UL Only */
155 #define R9A07G043_CRU_PRESETN		33	/* RZ/G2UL Only */
156 #define R9A07G043_CRU_ARESETN		34	/* RZ/G2UL Only */
157 #define R9A07G043_LCDC_RESET_N		35	/* RZ/G2UL Only */
162 #define R9A07G043_SRC_RST		40	/* RZ/G2UL Only */
192 #define R9A07G043_NCEPLDM_DTM_PWR_RST_N	70	/* RZ/Five Only */
193 #define R9A07G043_NCEPLDM_ARESETN	71	/* RZ/Five Only */
194 #define R9A07G043_NCEPLMT_POR_RSTN	72	/* RZ/Five Only */
195 #define R9A07G043_NCEPLMT_ARESETN	73	/* RZ/Five Only */
196 #define R9A07G043_NCEPLIC_ARESETN	74	/* RZ/Five Only */
197 #define R9A07G043_AX45MP_ARESETNM	75	/* RZ/Five Only */
198 #define R9A07G043_AX45MP_ARESETNS	76	/* RZ/Five Only */
199 #define R9A07G043_AX45MP_L2_RESETN	77	/* RZ/Five Only */
200 #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
201 #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */