Lines Matching +full:30 +full:- +full:35
1 /* SPDX-License-Identifier: GPL-2.0 */
34 #define CLK_MOUT_SCLK_JPEG_A 30
39 #define CLK_MOUT_SCLK_MMC0_D 35
231 #define CLK_MOUT_SCLK_DECON_VCLK_A 30
236 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
425 #define CLK_SCLK_SPI3 30
430 #define CLK_SCLK_UART1 35
495 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30
500 #define CLK_SCLK_TMU0 35
538 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30
543 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
672 #define CLK_DIV_SCLK_DSIM1_DISP 30
677 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35
792 #define CLK_PCLK_PMU_AUD 30
797 #define CLK_PCLK_AUD_I2S 35
912 #define CLK_SCLK_APOLLO 30
947 #define CLK_CNTCLK_ATLAS 30
952 #define CLK_HCLK_CSSYS 35
1067 #define CLK_ACLK_XIU_ISPEX0 30
1072 #define CLK_ACLK_SMMU_DIS0 35
1148 #define CLK_DIV_PCLK_CAM0_50 30
1153 #define CLK_DIV_PCLK_LITE_B 35
1285 #define CLK_ACLK_ASYNCAPBS_FD 30
1290 #define CLK_ACLK_ASYNCAXIM_CA5 35
1371 #define CLK_PCLK_SLIMSSS 35