Lines Matching +full:0 +full:x259
44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
73 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
74 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
75 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
76 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
77 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
78 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
79 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
80 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
81 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
82 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
87 #define DP_AUX_I2C_WRITE 0x0
88 #define DP_AUX_I2C_READ 0x1
89 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
90 #define DP_AUX_I2C_MOT 0x4
91 #define DP_AUX_NATIVE_WRITE 0x8
92 #define DP_AUX_NATIVE_READ 0x9
94 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
95 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
96 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
97 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
99 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
100 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
101 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
102 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
107 #define DP_DPCD_REV 0x000
108 # define DP_DPCD_REV_10 0x10
109 # define DP_DPCD_REV_11 0x11
110 # define DP_DPCD_REV_12 0x12
111 # define DP_DPCD_REV_13 0x13
112 # define DP_DPCD_REV_14 0x14
114 #define DP_MAX_LINK_RATE 0x001
116 #define DP_MAX_LANE_COUNT 0x002
117 # define DP_MAX_LANE_COUNT_MASK 0x1f
121 #define DP_MAX_DOWNSPREAD 0x003
122 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
127 #define DP_NORP 0x004
129 #define DP_DOWNSTREAMPORT_PRESENT 0x005
130 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
131 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
132 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
139 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
140 # define DP_CAP_ANSI_8B10B (1 << 0)
143 #define DP_DOWN_STREAM_PORT_COUNT 0x007
144 # define DP_PORT_COUNT_MASK 0x0f
148 #define DP_RECEIVE_PORT_0_CAP_0 0x008
152 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
154 #define DP_RECEIVE_PORT_1_CAP_0 0x00a
155 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
157 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
158 # define DP_I2C_SPEED_1K 0x01
159 # define DP_I2C_SPEED_5K 0x02
160 # define DP_I2C_SPEED_10K 0x04
161 # define DP_I2C_SPEED_100K 0x08
162 # define DP_I2C_SPEED_400K 0x10
163 # define DP_I2C_SPEED_1M 0x20
165 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
166 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
170 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
171 # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
174 #define DP_ADAPTER_CAP 0x00f /* 1.2 */
175 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
178 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
182 #define DP_FAUX_CAP 0x020 /* 1.2 */
183 # define DP_FAUX_CAP_1 (1 << 0)
185 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
186 # define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
190 #define DP_MSTM_CAP 0x021 /* 1.2 */
191 # define DP_MST_CAP (1 << 0)
194 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
197 #define DP_AV_GRANULARITY 0x023
198 # define DP_AG_FACTOR_MASK (0xf << 0)
199 # define DP_AG_FACTOR_3MS (0 << 0)
200 # define DP_AG_FACTOR_2MS (1 << 0)
201 # define DP_AG_FACTOR_1MS (2 << 0)
202 # define DP_AG_FACTOR_500US (3 << 0)
203 # define DP_AG_FACTOR_200US (4 << 0)
204 # define DP_AG_FACTOR_100US (5 << 0)
205 # define DP_AG_FACTOR_10US (6 << 0)
206 # define DP_AG_FACTOR_1US (7 << 0)
207 # define DP_VG_FACTOR_MASK (0xf << 4)
208 # define DP_VG_FACTOR_3MS (0 << 4)
215 #define DP_AUD_DEC_LAT0 0x024
216 #define DP_AUD_DEC_LAT1 0x025
218 #define DP_AUD_PP_LAT0 0x026
219 #define DP_AUD_PP_LAT1 0x027
221 #define DP_VID_INTER_LAT 0x028
223 #define DP_VID_PROG_LAT 0x029
225 #define DP_REP_LAT 0x02a
227 #define DP_AUD_DEL_INS0 0x02b
228 #define DP_AUD_DEL_INS1 0x02c
229 #define DP_AUD_DEL_INS2 0x02d
232 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
233 # define DP_ALPM_CAP (1 << 0)
235 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
236 # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
238 #define DP_GUID 0x030 /* 1.2 */
240 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
241 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
246 #define DP_DSC_REV 0x061
247 # define DP_DSC_MAJOR_MASK (0xf << 0)
248 # define DP_DSC_MINOR_MASK (0xf << 4)
249 # define DP_DSC_MAJOR_SHIFT 0
252 #define DP_DSC_RC_BUF_BLK_SIZE 0x062
253 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
254 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
255 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
256 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
258 #define DP_DSC_RC_BUF_SIZE 0x063
260 #define DP_DSC_SLICE_CAP_1 0x064
261 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
269 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
270 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
271 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
272 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
273 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
274 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
275 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
276 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
277 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
278 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
279 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
281 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
282 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
285 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
287 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
288 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
289 # define DP_DSC_MAX_BPP_DELTA_VERSION_MASK (0x3 << 5) /* eDP 1.5 & DP 2.0 */
292 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
293 # define DP_DSC_RGB (1 << 0)
299 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
304 #define DP_DSC_PEAK_THROUGHPUT 0x06B
305 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
306 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
307 # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
308 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
309 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
310 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
311 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
312 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
313 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
314 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
315 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
316 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
317 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
318 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
319 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
320 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
321 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
322 # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
323 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
325 # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
342 #define DP_DSC_MAX_SLICE_WIDTH 0x06C
346 #define DP_DSC_SLICE_CAP_2 0x06D
347 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
351 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
352 # define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f
353 # define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0
354 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
355 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
356 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
357 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
358 # define DP_DSC_BITS_PER_PIXEL_1_1 0x4
360 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
366 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
368 # define DP_PSR_SETUP_TIME_330 (0 << 1)
381 #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
382 #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
385 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
392 /* offset 0 */
393 #define DP_DOWNSTREAM_PORT_0 0x80
394 # define DP_DS_PORT_TYPE_MASK (7 << 0)
395 # define DP_DS_PORT_TYPE_DP 0
403 # define DP_DS_NON_EDID_MASK (0xf << 4)
413 # define DP_DS_MAX_BPC_MASK (3 << 0)
414 # define DP_DS_8BPC 0
420 # define DP_PCON_MAX_0GBPS (0 << 2)
433 # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
450 #define DP_MAX_DOWNSTREAM_PORTS 0x10
453 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
454 # define DP_FEC_CAPABLE (1 << 0)
458 #define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
461 #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */
462 #define DP_PCON_DSC_ENCODER 0x092
463 # define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
467 #define DP_PCON_DSC_VERSION 0x093
468 # define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
469 # define DP_PCON_DSC_MINOR_MASK (0xF << 4)
470 # define DP_PCON_DSC_MAJOR_SHIFT 0
474 #define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
475 # define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
476 # define DP_PCON_DSC_RC_BUF_BLK_1KB 0
482 #define DP_PCON_DSC_RC_BUF_SIZE 0x095
485 #define DP_PCON_DSC_SLICE_CAP_1 0x096
486 # define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
487 # define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
488 # define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
489 # define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
490 # define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
491 # define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
492 # define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
494 #define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
495 # define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
496 # define DP_PCON_DSC_DEPTH_9_BITS 0
506 #define DP_PCON_DSC_BLOCK_PREDICTION 0x098
507 # define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
509 #define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
510 # define DP_PCON_DSC_ENC_RGB (0x1 << 0)
511 # define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
512 # define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
513 # define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
514 # define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
516 #define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
517 # define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
518 # define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
519 # define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
521 #define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
524 #define DP_PCON_DSC_SLICE_CAP_2 0x09C
525 # define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
526 # define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
527 # define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
530 #define DP_PCON_DSC_BPP_INCR 0x09E
531 # define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
532 # define DP_PCON_DSC_ONE_16TH_BPP 0
539 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
540 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
541 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
544 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
547 #define DP_LINK_BW_SET 0x100
548 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
549 # define DP_LINK_BW_1_62 0x06
550 # define DP_LINK_BW_2_7 0x0a
551 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
552 # define DP_LINK_BW_8_1 0x1e /* 1.4 */
553 # define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
554 # define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
555 # define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
557 #define DP_LANE_COUNT_SET 0x101
558 # define DP_LANE_COUNT_MASK 0x0f
561 #define DP_TRAINING_PATTERN_SET 0x102
562 # define DP_TRAINING_PATTERN_DISABLE 0
568 # define DP_TRAINING_PATTERN_MASK 0x3
569 # define DP_TRAINING_PATTERN_MASK_1_4 0xf
572 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
581 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
586 #define DP_TRAINING_LANE0_SET 0x103
587 #define DP_TRAINING_LANE1_SET 0x104
588 #define DP_TRAINING_LANE2_SET 0x105
589 #define DP_TRAINING_LANE3_SET 0x106
591 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
592 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
594 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
595 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
596 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
597 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
600 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
608 # define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
610 #define DP_DOWNSPREAD_CTRL 0x107
615 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
616 # define DP_SET_ANSI_8B10B (1 << 0)
619 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
622 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
623 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
627 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
628 #define DP_LINK_QUAL_LANE1_SET 0x10c
629 #define DP_LINK_QUAL_LANE2_SET 0x10d
630 #define DP_LINK_QUAL_LANE3_SET 0x10e
631 # define DP_LINK_QUAL_PATTERN_DISABLE 0
640 # define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
641 # define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
642 # define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
643 # define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
644 # define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
645 # define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
646 # define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
647 # define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
648 # define DP_LINK_QUAL_PATTERN_SQUARE 0x48
650 #define DP_TRAINING_LANE0_1_SET2 0x10f
651 #define DP_TRAINING_LANE2_3_SET2 0x110
652 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
657 #define DP_MSTM_CTRL 0x111 /* 1.2 */
658 # define DP_MST_EN (1 << 0)
662 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
663 #define DP_AUDIO_DELAY1 0x113
664 #define DP_AUDIO_DELAY2 0x114
666 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
667 # define DP_LINK_RATE_SET_SHIFT 0
668 # define DP_LINK_RATE_SET_MASK (7 << 0)
670 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
671 # define DP_ALPM_ENABLE (1 << 0)
674 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
675 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
678 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
679 # define DP_PWR_NOT_NEEDED (1 << 0)
681 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
682 # define DP_FEC_READY (1 << 0)
684 # define DP_FEC_ERR_COUNT_DIS (0 << 1)
689 # define DP_FEC_LANE_0_SELECT (0 << 4)
694 #define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
695 #define DP_SDP_CRC16_128B132B_EN BIT(0)
697 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
698 # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
700 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
701 # define DP_DECOMPRESSION_EN (1 << 0)
702 #define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
704 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
705 # define DP_PSR_ENABLE BIT(0)
713 #define DP_ADAPTER_CTRL 0x1a0
714 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
716 #define DP_BRANCH_DEVICE_CTRL 0x1a1
717 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
719 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
720 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
721 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
724 #define DP_SINK_COUNT 0x200
726 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
729 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
730 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
738 #define DP_LANE0_1_STATUS 0x202
739 #define DP_LANE2_3_STATUS 0x203
740 # define DP_LANE_CR_DONE (1 << 0)
748 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
749 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
756 #define DP_SINK_STATUS 0x205
757 # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
762 #define DP_ADJUST_REQUEST_LANE0_1 0x206
763 #define DP_ADJUST_REQUEST_LANE2_3 0x207
764 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
765 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
766 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
768 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
770 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
774 # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
775 # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
776 # define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
779 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
780 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
781 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
782 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
784 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
786 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
789 #define DP_TEST_REQUEST 0x218
790 # define DP_TEST_LINK_TRAINING (1 << 0)
798 #define DP_TEST_LINK_RATE 0x219
799 # define DP_LINK_RATE_162 (0x6)
800 # define DP_LINK_RATE_27 (0xa)
802 #define DP_TEST_LANE_COUNT 0x220
804 #define DP_TEST_PATTERN 0x221
805 # define DP_NO_TEST_PATTERN 0x0
806 # define DP_COLOR_RAMP 0x1
807 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
808 # define DP_COLOR_SQUARE 0x3
810 #define DP_TEST_H_TOTAL_HI 0x222
811 #define DP_TEST_H_TOTAL_LO 0x223
813 #define DP_TEST_V_TOTAL_HI 0x224
814 #define DP_TEST_V_TOTAL_LO 0x225
816 #define DP_TEST_H_START_HI 0x226
817 #define DP_TEST_H_START_LO 0x227
819 #define DP_TEST_V_START_HI 0x228
820 #define DP_TEST_V_START_LO 0x229
822 #define DP_TEST_HSYNC_HI 0x22A
824 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
825 #define DP_TEST_HSYNC_WIDTH_LO 0x22B
827 #define DP_TEST_VSYNC_HI 0x22C
829 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
830 #define DP_TEST_VSYNC_WIDTH_LO 0x22D
832 #define DP_TEST_H_WIDTH_HI 0x22E
833 #define DP_TEST_H_WIDTH_LO 0x22F
835 #define DP_TEST_V_HEIGHT_HI 0x230
836 #define DP_TEST_V_HEIGHT_LO 0x231
838 #define DP_TEST_MISC0 0x232
839 # define DP_TEST_SYNC_CLOCK (1 << 0)
842 # define DP_COLOR_FORMAT_RGB (0 << 1)
845 # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
848 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
852 # define DP_TEST_BIT_DEPTH_6 (0 << 5)
858 #define DP_TEST_MISC1 0x233
859 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
862 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
864 #define DP_TEST_MISC0 0x232
866 #define DP_TEST_CRC_R_CR 0x240
867 #define DP_TEST_CRC_G_Y 0x242
868 #define DP_TEST_CRC_B_CB 0x244
870 #define DP_TEST_SINK_MISC 0x246
872 # define DP_TEST_COUNT_MASK 0xf
874 #define DP_PHY_TEST_PATTERN 0x248
875 # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
876 # define DP_PHY_TEST_PATTERN_NONE 0x0
877 # define DP_PHY_TEST_PATTERN_D10_2 0x1
878 # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
879 # define DP_PHY_TEST_PATTERN_PRBS7 0x3
880 # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
881 # define DP_PHY_TEST_PATTERN_CP2520 0x5
883 #define DP_PHY_SQUARE_PATTERN 0x249
885 #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
886 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
887 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
888 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
889 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
890 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
891 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
892 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
893 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
894 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
895 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
897 #define DP_TEST_RESPONSE 0x260
898 # define DP_TEST_ACK (1 << 0)
902 #define DP_TEST_EDID_CHECKSUM 0x261
904 #define DP_TEST_SINK 0x270
905 # define DP_TEST_SINK_START (1 << 0)
906 #define DP_TEST_AUDIO_MODE 0x271
907 #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
908 #define DP_TEST_AUDIO_PERIOD_CH1 0x273
909 #define DP_TEST_AUDIO_PERIOD_CH2 0x274
910 #define DP_TEST_AUDIO_PERIOD_CH3 0x275
911 #define DP_TEST_AUDIO_PERIOD_CH4 0x276
912 #define DP_TEST_AUDIO_PERIOD_CH5 0x277
913 #define DP_TEST_AUDIO_PERIOD_CH6 0x278
914 #define DP_TEST_AUDIO_PERIOD_CH7 0x279
915 #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
917 #define DP_FEC_STATUS 0x280 /* 1.4 */
918 # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
921 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
923 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
924 # define DP_FEC_ERROR_COUNT_MASK 0x7F
927 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
928 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
931 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
932 /* up to ID_SLOT_63 at 0x2ff */
935 #define DP_SOURCE_OUI 0x300
938 #define DP_SINK_OUI 0x400
941 #define DP_BRANCH_OUI 0x500
942 #define DP_BRANCH_ID 0x503
943 #define DP_BRANCH_REVISION_START 0x509
944 #define DP_BRANCH_HW_REV 0x509
945 #define DP_BRANCH_SW_REV 0x50A
948 #define DP_SET_POWER 0x600
949 # define DP_SET_POWER_D0 0x1
950 # define DP_SET_POWER_D3 0x2
951 # define DP_SET_POWER_MASK 0x3
952 # define DP_SET_POWER_D3_AUX_ON 0x5
955 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
956 # define DP_EDP_11 0x00
957 # define DP_EDP_12 0x01
958 # define DP_EDP_13 0x02
959 # define DP_EDP_14 0x03
960 # define DP_EDP_14a 0x04 /* eDP 1.4a */
961 # define DP_EDP_14b 0x05 /* eDP 1.4b */
963 #define DP_EDP_GENERAL_CAP_1 0x701
964 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
973 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
974 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
983 #define DP_EDP_GENERAL_CAP_2 0x703
984 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
987 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
988 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
989 # define DP_EDP_X_REGION_CAP_SHIFT 0
990 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
993 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
994 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
1000 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
1001 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
1002 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
1003 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
1004 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
1005 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
1013 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
1014 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
1016 #define DP_EDP_PWMGEN_BIT_COUNT 0x724
1017 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
1018 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
1019 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
1021 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
1023 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
1026 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
1027 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
1028 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
1030 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
1031 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
1032 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
1034 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
1035 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
1036 #define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734
1038 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
1039 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
1041 #define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */
1042 # define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
1043 # define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
1047 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
1048 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
1049 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
1050 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
1053 #define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */
1054 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */
1056 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
1057 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
1061 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
1062 # define RX_CAP_CHANGED (1 << 0)
1068 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
1069 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
1073 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
1074 # define DP_PSR_CAPS_CHANGE (1 << 0)
1076 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
1077 # define DP_PSR_SINK_INACTIVE 0
1083 # define DP_PSR_SINK_STATE_MASK 0x07
1085 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
1086 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
1087 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
1088 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
1091 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
1092 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
1100 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
1101 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
1103 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
1104 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
1105 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
1106 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
1109 #define DP_DP13_DPCD_REV 0x2200
1111 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
1112 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
1121 #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */
1122 # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0)
1126 #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
1127 # define DP_UHBR10 (1 << 0)
1131 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
1133 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1134 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
1135 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
1136 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02
1137 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03
1138 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04
1139 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05
1140 # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06
1142 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
1143 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
1146 #define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
1147 # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
1149 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
1150 # define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
1151 # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
1156 #define DP_CEC_TUNNELING_CAPABILITY 0x3000
1157 # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
1161 #define DP_CEC_TUNNELING_CONTROL 0x3001
1162 # define DP_CEC_TUNNELING_ENABLE (1 << 0)
1165 #define DP_CEC_RX_MESSAGE_INFO 0x3002
1166 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
1167 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
1173 #define DP_CEC_TX_MESSAGE_INFO 0x3003
1174 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
1175 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
1176 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
1180 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
1181 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
1188 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
1189 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
1197 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
1198 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1207 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1208 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1209 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1212 #define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
1213 # define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
1214 # define DP_PCON_ENABLE_MAX_BW_0GBPS 0
1223 # define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
1229 #define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
1230 # define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
1231 # define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
1238 # define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
1241 #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
1242 # define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
1246 #define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
1247 # define DP_PCON_HDMI_LINK_MODE (1 << 0)
1248 # define DP_PCON_HDMI_MODE_TMDS 0
1250 # define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
1258 #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
1259 # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
1260 #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
1261 # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
1265 #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
1266 # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
1268 # define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
1269 # define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
1278 #define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
1279 #define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
1280 #define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
1281 #define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
1282 # define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
1283 # define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
1288 * Valid Offsets to be added to Base : 0-127
1290 #define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
1293 * Offset-0 8LSBs of the Slice height.
1296 #define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
1299 * Offset-0 8LSBs of the Slice width.
1302 #define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
1305 * Offset-0 8LSBs of the bits_per_pixel.
1308 #define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
1311 #define DP_AUX_HDCP_BKSV 0x68000
1312 #define DP_AUX_HDCP_RI_PRIME 0x68005
1313 #define DP_AUX_HDCP_AKSV 0x68007
1314 #define DP_AUX_HDCP_AN 0x6800C
1315 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1316 #define DP_AUX_HDCP_BCAPS 0x68028
1318 # define DP_BCAPS_HDCP_CAPABLE BIT(0)
1319 #define DP_AUX_HDCP_BSTATUS 0x68029
1323 # define DP_BSTATUS_READY BIT(0)
1324 #define DP_AUX_HDCP_BINFO 0x6802A
1325 #define DP_AUX_HDCP_KSV_FIFO 0x6802C
1326 #define DP_AUX_HDCP_AINFO 0x6803B
1329 #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1330 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1331 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1332 #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1333 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1334 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1335 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1336 #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1337 #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1338 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1339 #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1340 #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1341 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1342 #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1343 #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1344 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1345 #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1346 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1347 #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1348 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1349 #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1350 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1351 #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1352 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1353 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1354 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1357 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1358 #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1359 #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1360 #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1361 #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1362 #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1363 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1364 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
1365 # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
1367 #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
1368 #define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */
1387 #define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
1388 #define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
1396 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1400 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1404 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1405 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1406 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1407 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1411 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1412 # define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
1415 #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */
1420 #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1424 #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1426 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1427 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1428 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1429 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1430 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1431 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1432 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1434 #define __DP_FEC1_BASE 0xf0290 /* 1.4 */
1435 #define __DP_FEC2_BASE 0xf0298 /* 1.4 */
1443 #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1447 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1448 #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1450 #define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
1452 #define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
1455 #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1456 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1475 #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1483 #define DP_PEER_DEVICE_NONE 0x0
1484 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1485 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
1486 #define DP_PEER_DEVICE_SST_SINK 0x3
1487 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1490 #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1491 #define DP_LINK_ADDRESS 0x01
1492 #define DP_CONNECTION_STATUS_NOTIFY 0x02
1493 #define DP_ENUM_PATH_RESOURCES 0x10
1494 #define DP_ALLOCATE_PAYLOAD 0x11
1495 #define DP_QUERY_PAYLOAD 0x12
1496 #define DP_RESOURCE_STATUS_NOTIFY 0x13
1497 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1498 #define DP_REMOTE_DPCD_READ 0x20
1499 #define DP_REMOTE_DPCD_WRITE 0x21
1500 #define DP_REMOTE_I2C_READ 0x22
1501 #define DP_REMOTE_I2C_WRITE 0x23
1502 #define DP_POWER_UP_PHY 0x24
1503 #define DP_POWER_DOWN_PHY 0x25
1504 #define DP_SINK_EVENT_NOTIFY 0x30
1505 #define DP_QUERY_STREAM_ENC_STATUS 0x38
1506 #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1511 #define DP_SIDEBAND_REPLY_ACK 0x00
1512 #define DP_SIDEBAND_REPLY_NAK 0x01
1515 #define DP_NAK_WRITE_FAILURE 0x01
1516 #define DP_NAK_INVALID_READ 0x02
1517 #define DP_NAK_CRC_FAILURE 0x03
1518 #define DP_NAK_BAD_PARAM 0x04
1519 #define DP_NAK_DEFER 0x05
1520 #define DP_NAK_LINK_FAILURE 0x06
1521 #define DP_NAK_NO_RESOURCES 0x07
1522 #define DP_NAK_DPCD_FAIL 0x08
1523 #define DP_NAK_I2C_NAK 0x09
1524 #define DP_NAK_ALLOCATE_FAIL 0x0a
1532 #define DP_MST_PHYSICAL_PORT_0 0
1535 #define DP_LINK_CONSTANT_N_VALUE 0x8000
1538 #define DP_BRANCH_OUI_HEADER_SIZE 0xc
1539 #define DP_RECEIVER_CAP_SIZE 0xf
1540 #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
1546 #define DP_SDP_AUDIO_TIMESTAMP 0x01
1547 #define DP_SDP_AUDIO_STREAM 0x02
1548 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1549 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1550 #define DP_SDP_ISRC 0x06 /* DP 1.2 */
1551 #define DP_SDP_VSC 0x07 /* DP 1.2 */
1552 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1553 #define DP_SDP_PPS 0x10 /* DP 1.4 */
1554 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1555 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1556 /* 0x80+ CEA-861 infoframe types */
1558 #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
1564 * @HB2: Secondary Data Packet Specific header, Byte 0
1574 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
1575 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1576 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1583 * db[0]: Stereo Interface
1584 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1585 * db[2]: CRC value bits 7:0 of the R or Cr component
1587 * db[4]: CRC value bits 7:0 of the G or Y component
1589 * db[6]: CRC value bits 7:0 of the B or Cb component
1593 * db[0] - db[15]: Reserved
1604 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1618 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1624 DP_PIXELFORMAT_RGB = 0,
1625 DP_PIXELFORMAT_YUV444 = 0x1,
1626 DP_PIXELFORMAT_YUV422 = 0x2,
1627 DP_PIXELFORMAT_YUV420 = 0x3,
1628 DP_PIXELFORMAT_Y_ONLY = 0x4,
1629 DP_PIXELFORMAT_RAW = 0x5,
1630 DP_PIXELFORMAT_RESERVED = 0x6,
1658 DP_COLORIMETRY_DEFAULT = 0,
1659 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1660 DP_COLORIMETRY_BT709_YCC = 0x1,
1661 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1662 DP_COLORIMETRY_XVYCC_601 = 0x2,
1663 DP_COLORIMETRY_OPRGB = 0x3,
1664 DP_COLORIMETRY_XVYCC_709 = 0x3,
1665 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1666 DP_COLORIMETRY_SYCC_601 = 0x4,
1667 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1668 DP_COLORIMETRY_OPYCC_601 = 0x5,
1669 DP_COLORIMETRY_BT2020_RGB = 0x6,
1670 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1671 DP_COLORIMETRY_BT2020_YCC = 0x7,
1685 DP_DYNAMIC_RANGE_VESA = 0,
1704 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1705 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1706 DP_CONTENT_TYPE_PHOTO = 0x02,
1707 DP_CONTENT_TYPE_VIDEO = 0x03,
1708 DP_CONTENT_TYPE_GAME = 0x04,