1 // SPDX-License-Identifier: GPL-2.0
3  * Driver for STM32 Independent Watchdog
33 #define KR_KEY_RELOAD	0xAAAA /* reload counter enable */
48 #define SR_RVU	BIT(1) /* Watchdog counter reload value update */
94 	dev_dbg(wdd->parent, "%s\n", __func__);  in stm32_iwdg_start()
96 	tout = clamp_t(unsigned int, wdd->timeout,  in stm32_iwdg_start()
97 		       wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);  in stm32_iwdg_start()
99 	presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);  in stm32_iwdg_start()
103 	iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;  in stm32_iwdg_start()
104 	iwdg_rlr = ((tout * wdt->rate) / presc) - 1;  in stm32_iwdg_start()
107 	reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);  in stm32_iwdg_start()
110 	reg_write(wdt->regs, IWDG_PR, iwdg_pr);  in stm32_iwdg_start()
111 	reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);  in stm32_iwdg_start()
112 	reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);  in stm32_iwdg_start()
115 	ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,  in stm32_iwdg_start()
119 		dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");  in stm32_iwdg_start()
124 	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);  in stm32_iwdg_start()
133 	dev_dbg(wdd->parent, "%s\n", __func__);  in stm32_iwdg_ping()
136 	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);  in stm32_iwdg_ping()
144 	dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);  in stm32_iwdg_set_timeout()
146 	wdd->timeout = timeout;  in stm32_iwdg_set_timeout()
162 	struct device *dev = &pdev->dev;  in stm32_iwdg_clk_init()
165 	wdt->clk_lsi = devm_clk_get(dev, "lsi");  in stm32_iwdg_clk_init()
166 	if (IS_ERR(wdt->clk_lsi))  in stm32_iwdg_clk_init()
167 		return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n");  in stm32_iwdg_clk_init()
170 	if (wdt->data->has_pclk) {  in stm32_iwdg_clk_init()
171 		wdt->clk_pclk = devm_clk_get(dev, "pclk");  in stm32_iwdg_clk_init()
172 		if (IS_ERR(wdt->clk_pclk))  in stm32_iwdg_clk_init()
173 			return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),  in stm32_iwdg_clk_init()
176 		ret = clk_prepare_enable(wdt->clk_pclk);  in stm32_iwdg_clk_init()
183 					       wdt->clk_pclk);  in stm32_iwdg_clk_init()
188 	ret = clk_prepare_enable(wdt->clk_lsi);  in stm32_iwdg_clk_init()
194 				       wdt->clk_lsi);  in stm32_iwdg_clk_init()
198 	wdt->rate = clk_get_rate(wdt->clk_lsi);  in stm32_iwdg_clk_init()
207 	.identity	= "STM32 Independent Watchdog",
218 	{ .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
219 	{ .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
226 	struct device *dev = &pdev->dev;  in stm32_iwdg_probe()
233 		return -ENOMEM;  in stm32_iwdg_probe()
235 	wdt->data = of_device_get_match_data(&pdev->dev);  in stm32_iwdg_probe()
236 	if (!wdt->data)  in stm32_iwdg_probe()
237 		return -ENODEV;  in stm32_iwdg_probe()
239 	/* This is the timer base. */  in stm32_iwdg_probe()
240 	wdt->regs = devm_platform_ioremap_resource(pdev, 0);  in stm32_iwdg_probe()
241 	if (IS_ERR(wdt->regs))  in stm32_iwdg_probe()
242 		return PTR_ERR(wdt->regs);  in stm32_iwdg_probe()
249 	wdd = &wdt->wdd;  in stm32_iwdg_probe()
250 	wdd->parent = dev;  in stm32_iwdg_probe()
251 	wdd->info = &stm32_iwdg_info;  in stm32_iwdg_probe()
252 	wdd->ops = &stm32_iwdg_ops;  in stm32_iwdg_probe()
253 	wdd->timeout = DEFAULT_TIMEOUT;  in stm32_iwdg_probe()
254 	wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);  in stm32_iwdg_probe()
255 	wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *  in stm32_iwdg_probe()
256 				    1000) / wdt->rate;  in stm32_iwdg_probe()
264 	 * (Means U-Boot/bootloaders leaves the watchdog running)  in stm32_iwdg_probe()
277 		set_bit(WDOG_HW_RUNNING, &wdd->status);  in stm32_iwdg_probe()
299 MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");