51 	u32 control_status_reg;  in xilinx_wdt_start()  local
63 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_start()
64 	control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);  in xilinx_wdt_start()
66 	iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),  in xilinx_wdt_start()
80 	u32 control_status_reg;  in xilinx_wdt_stop()  local
85 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_stop()
87 	iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),  in xilinx_wdt_stop()
103 	u32 control_status_reg;  in xilinx_wdt_keepalive()  local
108 	control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_keepalive()
109 	control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);  in xilinx_wdt_keepalive()
110 	iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);  in xilinx_wdt_keepalive()