drivers/watchdog/mtk_wdt.c

1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dt-bindings/reset/mt2712-resets.h>
13 #include <dt-bindings/reset/mediatek,mt6735-wdt.h>
14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
15 #include <dt-bindings/reset/mt7986-resets.h>
16 #include <dt-bindings/reset/mt8183-resets.h>
17 #include <dt-bindings/reset/mt8186-resets.h>
18 #include <dt-bindings/reset/mt8188-resets.h>
19 #include <dt-bindings/reset/mt8192-resets.h>
20 #include <dt-bindings/reset/mt8195-resets.h>
30 #include <linux/reset-controller.h>
62 #define DRV_NAME		"mtk-wdt"
125 	spin_lock_irqsave(&data->lock, flags);
127 	tmp = readl(data->wdt_base + WDT_SWSYSRST);
133 	writel(tmp, data->wdt_base + WDT_SWSYSRST);
135 	spin_unlock_irqrestore(&data->lock, flags);
167 	.reset = toprgu_reset,
176 	spin_lock_init(&mtk_wdt->lock);
178 	mtk_wdt->rcdev.owner = THIS_MODULE;
179 	mtk_wdt->rcdev.nr_resets = rst_num;
180 	mtk_wdt->rcdev.ops = &toprgu_reset_ops;
181 	mtk_wdt->rcdev.of_node = pdev->dev.of_node;
182 	ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
184 		dev_err(&pdev->dev,
185 			"couldn't register wdt reset controller: %d\n", ret);
196 	wdt_base = mtk_wdt->wdt_base;
198 	/* Enable reset in order to issue a system reset instead of an IRQ */
214 	void __iomem *wdt_base = mtk_wdt->wdt_base;
225 	void __iomem *wdt_base = mtk_wdt->wdt_base;
228 	wdt_dev->timeout = timeout;
233 	if (wdt_dev->pretimeout)
234 		wdt_dev->pretimeout = timeout / 2;
240 	reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
254 	wdt_base = mtk_wdt->wdt_base;
257 		set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
258 		mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
265 	void __iomem *wdt_base = mtk_wdt->wdt_base;
280 	void __iomem *wdt_base = mtk_wdt->wdt_base;
283 	ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
288 	if (wdt_dev->pretimeout)
292 	if (mtk_wdt->disable_wdt_extrst)
294 	if (mtk_wdt->reset_by_toprgu)
306 	void __iomem *wdt_base = mtk_wdt->wdt_base;
309 	if (timeout && !wdd->pretimeout) {
310 		wdd->pretimeout = wdd->timeout / 2;
312 	} else if (!timeout && wdd->pretimeout) {
313 		wdd->pretimeout = 0;
322 	return mtk_wdt_set_timeout(wdd, wdd->timeout);
361 	struct device *dev = &pdev->dev;
368 		return -ENOMEM;
372 	mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
373 	if (IS_ERR(mtk_wdt->wdt_base))
374 		return PTR_ERR(mtk_wdt->wdt_base);
378 		err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
379 				       &mtk_wdt->wdt_dev);
383 		mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
384 		mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
386 		if (irq == -EPROBE_DEFER)
387 			return -EPROBE_DEFER;
389 		mtk_wdt->wdt_dev.info = &mtk_wdt_info;
392 	mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
393 	mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
394 	mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
395 	mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
396 	mtk_wdt->wdt_dev.parent = dev;
398 	watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
399 	watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
400 	watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
402 	watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
404 	mtk_wdt_init(&mtk_wdt->wdt_dev);
406 	watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
407 	err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
412 		 mtk_wdt->wdt_dev.timeout, nowayout);
417 						       wdt_data->toprgu_sw_rst_num);
422 	mtk_wdt->disable_wdt_extrst =
423 		of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
425 	mtk_wdt->reset_by_toprgu =
426 		of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");
435 	if (watchdog_active(&mtk_wdt->wdt_dev))
436 		mtk_wdt_stop(&mtk_wdt->wdt_dev);
445 	if (watchdog_active(&mtk_wdt->wdt_dev)) {
446 		mtk_wdt_start(&mtk_wdt->wdt_dev);
447 		mtk_wdt_ping(&mtk_wdt->wdt_dev);
454 	{ .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
455 	{ .compatible = "mediatek,mt6589-wdt" },
456 	{ .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data },
457 	{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
458 	{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
459 	{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
460 	{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
461 	{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
462 	{ .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
463 	{ .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },