Lines Matching refs:vgabase
197 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
205 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
276 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); in s3fb_setup_ddc_bus()
278 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); in s3fb_setup_ddc_bus()
280 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); in s3fb_setup_ddc_bus()
317 svga_tilecursor(par->state.vgabase, info, cursor); in s3fb_tilecursor()
474 regval = vga_r(par->state.vgabase, VGA_MIS_R); in s3_set_pixclock()
475 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in s3_set_pixclock()
484 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ in s3_set_pixclock()
485 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ in s3_set_pixclock()
487 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); in s3_set_pixclock()
488 vga_wseq(par->state.vgabase, 0x13, m - 2); in s3_set_pixclock()
493 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
496 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
508 void __iomem *vgabase = par->state.vgabase; in s3fb_open() local
511 par->state.vgabase = vgabase; in s3fb_open()
646 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3fb_set_par()
647 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3fb_set_par()
648 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3fb_set_par()
649 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in s3fb_set_par()
652 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_set_par()
653 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in s3fb_set_par()
656 svga_set_default_gfx_regs(par->state.vgabase); in s3fb_set_par()
657 svga_set_default_atc_regs(par->state.vgabase); in s3fb_set_par()
658 svga_set_default_seq_regs(par->state.vgabase); in s3fb_set_par()
659 svga_set_default_crt_regs(par->state.vgabase); in s3fb_set_par()
660 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); in s3fb_set_par()
661 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); in s3fb_set_par()
664 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ in s3fb_set_par()
665 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab… in s3fb_set_par()
669 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ in s3fb_set_par()
670 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ in s3fb_set_par()
672 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ in s3fb_set_par()
682 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); in s3fb_set_par()
690 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ in s3fb_set_par()
691 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ in s3fb_set_par()
692 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ in s3fb_set_par()
693 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ in s3fb_set_par()
696 vga_wcrt(par->state.vgabase, 0x3A, 0x35); in s3fb_set_par()
697 svga_wattr(par->state.vgabase, 0x33, 0x00); in s3fb_set_par()
700 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in s3fb_set_par()
702 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in s3fb_set_par()
705 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); in s3fb_set_par()
707 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); in s3fb_set_par()
710 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); in s3fb_set_par()
712 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); in s3fb_set_par()
718 vga_wcrt(par->state.vgabase, 0x86, 0x80); in s3fb_set_par()
719 vga_wcrt(par->state.vgabase, 0x90, 0x00); in s3fb_set_par()
724 vga_wcrt(par->state.vgabase, 0x50, 0x00); in s3fb_set_par()
725 vga_wcrt(par->state.vgabase, 0x67, 0x50); in s3fb_set_par()
727 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); in s3fb_set_par()
728 vga_wcrt(par->state.vgabase, 0x66, 0x90); in s3fb_set_par()
741 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); in s3fb_set_par()
742 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); in s3fb_set_par()
744 vga_wcrt(par->state.vgabase, 0x66, 0x81); in s3fb_set_par()
753 vga_wcrt(par->state.vgabase, 0x34, 0x00); in s3fb_set_par()
755 vga_wcrt(par->state.vgabase, 0x34, 0x10); in s3fb_set_par()
757 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); in s3fb_set_par()
765 svga_set_textmode_vga_regs(par->state.vgabase); in s3fb_set_par()
768 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
769 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
772 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
776 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); in s3fb_set_par()
781 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in s3fb_set_par()
784 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
785 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
788 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
794 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
795 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
798 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
802 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
810 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
812 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); in s3fb_set_par()
820 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
822 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
824 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
826 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
829 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
833 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
834 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
848 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
850 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
852 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
854 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
857 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
861 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
862 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
875 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
879 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); in s3fb_set_par()
880 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
888 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); in s3fb_set_par()
889 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); in s3fb_set_par()
893 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, in s3fb_set_par()
901 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); in s3fb_set_par()
907 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); in s3fb_set_par()
913 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in s3fb_set_par()
914 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_set_par()
989 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
990 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_blank()
994 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
995 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
999 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); in s3fb_blank()
1000 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1004 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); in s3fb_blank()
1005 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1009 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); in s3fb_blank()
1010 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1037 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); in s3fb_pan_display()
1068 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification()
1069 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); in s3_identification()
1070 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); in s3_identification()
1085 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1094 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1103 switch (vga_rcrt(par->state.vgabase, 0x2f)) { in s3_identification()
1182 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; in s3_pci_probe()
1185 cr38 = vga_rcrt(par->state.vgabase, 0x38); in s3_pci_probe()
1186 cr39 = vga_rcrt(par->state.vgabase, 0x39); in s3_pci_probe()
1187 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3_pci_probe()
1188 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3_pci_probe()
1189 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3_pci_probe()
1193 par->rev = vga_rcrt(par->state.vgabase, 0x2f); in s3_pci_probe()
1199 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1242 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1256 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1257 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1261 vga_wcrt(par->state.vgabase, 0x38, cr38); in s3_pci_probe()
1262 vga_wcrt(par->state.vgabase, 0x39, cr39); in s3_pci_probe()
1279 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ in s3_pci_probe()
1357 vga_rcrt(par->state.vgabase, 0x2d), in s3_pci_probe()
1358 vga_rcrt(par->state.vgabase, 0x2e), in s3_pci_probe()
1359 vga_rcrt(par->state.vgabase, 0x2f), in s3_pci_probe()
1360 vga_rcrt(par->state.vgabase, 0x30)); in s3_pci_probe()