145 static inline u32 pm2_RD(struct pm2fb_par *p, s32 off)  in pm2_RD()  argument
147 	return fb_readl(p->v_regs + off);  in pm2_RD()
150 static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v)  in pm2_WR()  argument
152 	fb_writel(v, p->v_regs + off);  in pm2_WR()
155 static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx)  in pm2_RDAC_RD()  argument
157 	pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);  in pm2_RDAC_RD()
159 	return pm2_RD(p, PM2R_RD_INDEXED_DATA);  in pm2_RDAC_RD()
162 static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx)  in pm2v_RDAC_RD()  argument
164 	pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);  in pm2v_RDAC_RD()
166 	return pm2_RD(p,  PM2VR_RD_INDEXED_DATA);  in pm2v_RDAC_RD()
169 static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)  in pm2_RDAC_WR()  argument
171 	pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);  in pm2_RDAC_WR()
173 	pm2_WR(p, PM2R_RD_INDEXED_DATA, v);  in pm2_RDAC_WR()
177 static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)  in pm2v_RDAC_WR()  argument
179 	pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);  in pm2v_RDAC_WR()
181 	pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);  in pm2v_RDAC_WR()
186 #define WAIT_FIFO(p, a)  argument
188 static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a)  in WAIT_FIFO()  argument
190 	while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a)  in WAIT_FIFO()
257 	unsigned char p;  in pm2_mnp()  local
267 				for (p = 0; p < 5; p++, f >>= 1) {  in pm2_mnp()
273 						*pp = p;  in pm2_mnp()
286 	unsigned char p;  in pm2v_mnp()  local
293 			for (p = 0; p < 2; p++) {  in pm2v_mnp()
294 				f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m;  in pm2v_mnp()
299 					*pp = p;  in pm2v_mnp()
306 static void clear_palette(struct pm2fb_par *p)  in clear_palette()  argument
310 	WAIT_FIFO(p, 1);  in clear_palette()
311 	pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);  in clear_palette()
314 		WAIT_FIFO(p, 3);  in clear_palette()
315 		pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);  in clear_palette()
316 		pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);  in clear_palette()
317 		pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);  in clear_palette()
321 static void reset_card(struct pm2fb_par *p)  in reset_card()  argument
323 	if (p->type == PM2_TYPE_PERMEDIA2V)  in reset_card()
324 		pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);  in reset_card()
325 	pm2_WR(p, PM2R_RESET_STATUS, 0);  in reset_card()
327 	while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)  in reset_card()
332 	pm2_WR(p, PM2R_FIFO_DISCON, 1);  in reset_card()
337 	WAIT_FIFO(p, 3);  in reset_card()
338 	pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);  in reset_card()
339 	pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);  in reset_card()
341 	pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);  in reset_card()
344 static void reset_config(struct pm2fb_par *p)  in reset_config()  argument
346 	WAIT_FIFO(p, 53);  in reset_config()
347 	pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &  in reset_config()
349 	pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));  in reset_config()
350 	pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));  in reset_config()
351 	pm2_WR(p, PM2R_FIFO_CONTROL, 0);  in reset_config()
352 	pm2_WR(p, PM2R_APERTURE_ONE, 0);  in reset_config()
353 	pm2_WR(p, PM2R_APERTURE_TWO, 0);  in reset_config()
354 	pm2_WR(p, PM2R_RASTERIZER_MODE, 0);  in reset_config()
355 	pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);  in reset_config()
356 	pm2_WR(p, PM2R_LB_READ_FORMAT, 0);  in reset_config()
357 	pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);  in reset_config()
358 	pm2_WR(p, PM2R_LB_READ_MODE, 0);  in reset_config()
359 	pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);  in reset_config()
360 	pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);  in reset_config()
361 	pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);  in reset_config()
362 	pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);  in reset_config()
363 	pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);  in reset_config()
364 	pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));  in reset_config()
365 	pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));  in reset_config()
366 	pm2_WR(p, PM2R_FB_READ_PIXEL, 0);  in reset_config()
367 	pm2_WR(p, PM2R_DITHER_MODE, 0);  in reset_config()
368 	pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);  in reset_config()
369 	pm2_WR(p, PM2R_DEPTH_MODE, 0);  in reset_config()
370 	pm2_WR(p, PM2R_STENCIL_MODE, 0);  in reset_config()
371 	pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);  in reset_config()
372 	pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);  in reset_config()
373 	pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);  in reset_config()
374 	pm2_WR(p, PM2R_YUV_MODE, 0);  in reset_config()
375 	pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);  in reset_config()
376 	pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);  in reset_config()
377 	pm2_WR(p, PM2R_FOG_MODE, 0);  in reset_config()
378 	pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);  in reset_config()
379 	pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);  in reset_config()
380 	pm2_WR(p, PM2R_STATISTICS_MODE, 0);  in reset_config()
381 	pm2_WR(p, PM2R_SCISSOR_MODE, 0);  in reset_config()
382 	pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);  in reset_config()
383 	pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);  in reset_config()
384 	switch (p->type) {  in reset_config()
386 		pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */  in reset_config()
387 		pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);  in reset_config()
388 		pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);  in reset_config()
389 		pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);  in reset_config()
390 		pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);  in reset_config()
391 		pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);  in reset_config()
392 		pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);  in reset_config()
393 		pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);  in reset_config()
396 		pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */  in reset_config()
401 static void set_aperture(struct pm2fb_par *p, u32 depth)  in set_aperture()  argument
408 	WAIT_FIFO(p, 2);  in set_aperture()
410 	pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);  in set_aperture()
420 		pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);  in set_aperture()
423 		pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);  in set_aperture()
426 		pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);  in set_aperture()
432 	pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);  in set_aperture()
435 static void set_color(struct pm2fb_par *p, unsigned char regno,  in set_color()  argument
438 	WAIT_FIFO(p, 4);  in set_color()
439 	pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);  in set_color()
441 	pm2_WR(p, PM2R_RD_PALETTE_DATA, r);  in set_color()
443 	pm2_WR(p, PM2R_RD_PALETTE_DATA, g);  in set_color()
445 	pm2_WR(p, PM2R_RD_PALETTE_DATA, b);  in set_color()
451 	unsigned char m, n, p;  in set_memclock()  local
455 		pm2v_mnp(clk/2, &m, &n, &p);  in set_memclock()
461 		pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);  in set_memclock()
470 		pm2_mnp(clk, &m, &n, &p);  in set_memclock()
475 		pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);  in set_memclock()
488 	unsigned char m, n, p;  in set_pixclock()  local
492 		pm2_mnp(clk, &m, &n, &p);  in set_pixclock()
497 		pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);  in set_pixclock()
505 		pm2v_mnp(clk/2, &m, &n, &p);  in set_pixclock()
510 		pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);  in set_pixclock()
516 static void set_video(struct pm2fb_par *p, u32 video)  in set_video()  argument
532 	WAIT_FIFO(p, 3);  in set_video()
533 	pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);  in set_video()
535 	switch (p->type) {  in set_video()
542 		pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);  in set_video()
550 		pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);  in set_video()
976 	struct pm2fb_par *p = info->par;  in pm2fb_pan_display()  local
983 	WAIT_FIFO(p, 1);  in pm2fb_pan_display()
984 	pm2_WR(p, PM2R_SCREEN_BASE, base);  in pm2fb_pan_display()