135 static u8 hwa742_read_reg(u8 reg)  in hwa742_read_reg()  function
201 	b = hwa742_read_reg(HWA742_NDP_CTRL);  in enable_tearsync()
230 	b = hwa742_read_reg(HWA742_NDP_CTRL);  in disable_tearsync()
769 	pix_clk_src = hwa742_read_reg(HWA742_CLK_SRC_REG);  in calc_hwa742_clk_rates()
773 		sys_div = (hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x3f) + 1;  in calc_hwa742_clk_rates()
774 		sys_mul = (hwa742_read_reg(HWA742_PLL_4_REG) & 0x7f) + 1;  in calc_hwa742_clk_rates()
798 	hsw = hwa742_read_reg(HWA742_HS_W_REG);  in setup_tearsync()
799 	vsw = hwa742_read_reg(HWA742_VS_W_REG);  in setup_tearsync()
805 	hdisp = (hwa742_read_reg(HWA742_H_DISP_REG) & 0x7f) * 8;  in setup_tearsync()
806 	vdisp = hwa742_read_reg(HWA742_V_DISP_1_REG) +  in setup_tearsync()
807 		((hwa742_read_reg(HWA742_V_DISP_2_REG) & 0x3) << 8);  in setup_tearsync()
809 	hndp = hwa742_read_reg(HWA742_H_NDP_REG) & 0x7f;  in setup_tearsync()
810 	vndp = hwa742_read_reg(HWA742_V_NDP_REG);  in setup_tearsync()
879 	b = hwa742_read_reg(HWA742_NDP_CTRL);  in setup_tearsync()
926 		if (hwa742_read_reg(HWA742_PLL_DIV_REG) & (1 << 7))  in hwa742_resume()
973 	rev = hwa742_read_reg(HWA742_REV_CODE_REG);  in hwa742_init()
981 	if (!(hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x80)) {  in hwa742_init()
1019 	conf = hwa742_read_reg(HWA742_CONFIG_REG);  in hwa742_init()