Lines Matching refs:TVP3026_XPLLADDR
204 #define TVP3026_XPLLADDR 0x2C macro
455 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC); in ti3026_setMCLK()
457 outTi3026(minfo, TVP3026_XPLLADDR, 0xFD); in ti3026_setMCLK()
459 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE); in ti3026_setMCLK()
463 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE); in ti3026_setMCLK()
467 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC); in ti3026_setMCLK()
487 outTi3026(minfo, TVP3026_XPLLADDR, 0xFB); in ti3026_setMCLK()
491 outTi3026(minfo, TVP3026_XPLLADDR, 0xF3); in ti3026_setMCLK()
523 outTi3026(minfo, TVP3026_XPLLADDR, 0xFE); in ti3026_setMCLK()
527 outTi3026(minfo, TVP3026_XPLLADDR, 0xFC); in ti3026_setMCLK()
592 outTi3026(minfo, TVP3026_XPLLADDR, 0x00); in Ti3026_restore()
595 outTi3026(minfo, TVP3026_XPLLADDR, 0x15); in Ti3026_restore()
598 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A); in Ti3026_restore()
610 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A); in Ti3026_restore()
614 outTi3026(minfo, TVP3026_XPLLADDR, 0x00); in Ti3026_restore()
620 outTi3026(minfo, TVP3026_XPLLADDR, 0x3F); in Ti3026_restore()
636 outTi3026(minfo, TVP3026_XPLLADDR, 0x00); in Ti3026_restore()
644 outTi3026(minfo, TVP3026_XPLLADDR, 0x3F); in Ti3026_restore()
724 outTi3026(minfo, TVP3026_XPLLADDR, 0x2A); in Ti3026_preinit()