Lines Matching +full:0 +full:x100d0000
120 #define REG_DDC_DRIVE 0x62
121 #define REG_DDC_STATE 0x63
130 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL); in i740fb_ddc_setscl()
138 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA); in i740fb_ddc_setsda()
145 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL); in i740fb_ddc_getscl()
154 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA); in i740fb_ddc_getsda()
190 return 0; in i740fb_open()
198 if (par->ref_count == 0) { in i740fb_release()
207 return 0; in i740fb_release()
225 wm = 0x18120000; in i740_calc_fifo()
227 wm = 0x16110000; in i740_calc_fifo()
229 wm = 0x120E0000; in i740_calc_fifo()
231 wm = 0x100D0000; in i740_calc_fifo()
237 wm = 0x2C1D0000; in i740_calc_fifo()
239 wm = 0x2C180000; in i740_calc_fifo()
241 wm = 0x24160000; in i740_calc_fifo()
243 wm = 0x18120000; in i740_calc_fifo()
245 wm = 0x16110000; in i740_calc_fifo()
247 wm = 0x13100000; in i740_calc_fifo()
249 wm = 0x120E0000; in i740_calc_fifo()
252 wm = 0x28200000; in i740_calc_fifo()
254 wm = 0x2A1E0000; in i740_calc_fifo()
256 wm = 0x2B1A0000; in i740_calc_fifo()
258 wm = 0x2C180000; in i740_calc_fifo()
260 wm = 0x24180000; in i740_calc_fifo()
262 wm = 0x18120000; in i740_calc_fifo()
264 wm = 0x16110000; in i740_calc_fifo()
266 wm = 0x13100000; in i740_calc_fifo()
268 wm = 0x120E0000; in i740_calc_fifo()
274 wm = 0x31200000; in i740_calc_fifo()
276 wm = 0x2E200000; in i740_calc_fifo()
278 wm = 0x2C1D0000; in i740_calc_fifo()
280 wm = 0x25180000; in i740_calc_fifo()
282 wm = 0x24160000; in i740_calc_fifo()
284 wm = 0x18120000; in i740_calc_fifo()
286 wm = 0x16110000; in i740_calc_fifo()
288 wm = 0x13100000; in i740_calc_fifo()
291 wm = 0x311F0000; in i740_calc_fifo()
293 wm = 0x2C1D0000; in i740_calc_fifo()
295 wm = 0x25180000; in i740_calc_fifo()
297 wm = 0x24160000; in i740_calc_fifo()
299 wm = 0x18120000; in i740_calc_fifo()
301 wm = 0x16110000; in i740_calc_fifo()
303 wm = 0x13100000; in i740_calc_fifo()
309 wm = 0x2A200000; in i740_calc_fifo()
311 wm = 0x281A0000; in i740_calc_fifo()
313 wm = 0x25180000; in i740_calc_fifo()
315 wm = 0x18120000; in i740_calc_fifo()
317 wm = 0x16110000; in i740_calc_fifo()
320 wm = 0x29200000; in i740_calc_fifo()
322 wm = 0x281A0000; in i740_calc_fifo()
324 wm = 0x25180000; in i740_calc_fifo()
326 wm = 0x18120000; in i740_calc_fifo()
328 wm = 0x16110000; in i740_calc_fifo()
351 int m_best = 0, n_best = 0, p_best = 0; in i740_calc_vclk()
386 par->video_clk2_m = (m_best - 2) & 0xFF; in i740_calc_vclk()
387 par->video_clk2_n = (n_best - 2) & 0xFF; in i740_calc_vclk()
506 par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F) in i740fb_decode_var()
507 | ((((xres + right + hslen) >> 3) & 0x20) << 2); in i740fb_decode_var()
508 par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F) in i740fb_decode_var()
509 | 0x80; in i740fb_decode_var()
513 r7 = 0x10; /* disable linecompare */ in i740fb_decode_var()
514 if (ytotal & 0x100) in i740fb_decode_var()
515 r7 |= 0x01; in i740fb_decode_var()
516 if (ytotal & 0x200) in i740fb_decode_var()
517 r7 |= 0x20; in i740fb_decode_var()
519 par->crtc[VGA_CRTC_PRESET_ROW] = 0; in i740fb_decode_var()
520 par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */ in i740fb_decode_var()
522 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80; in i740fb_decode_var()
523 par->crtc[VGA_CRTC_CURSOR_START] = 0x00; in i740fb_decode_var()
524 par->crtc[VGA_CRTC_CURSOR_END] = 0x00; in i740fb_decode_var()
525 par->crtc[VGA_CRTC_CURSOR_HI] = 0x00; in i740fb_decode_var()
526 par->crtc[VGA_CRTC_CURSOR_LO] = 0x00; in i740fb_decode_var()
528 if ((yres-1) & 0x100) in i740fb_decode_var()
529 r7 |= 0x02; in i740fb_decode_var()
530 if ((yres-1) & 0x200) in i740fb_decode_var()
531 r7 |= 0x40; in i740fb_decode_var()
535 if ((yres + lower - 1) & 0x100) in i740fb_decode_var()
536 r7 |= 0x0C; in i740fb_decode_var()
537 if ((yres + lower - 1) & 0x200) { in i740fb_decode_var()
538 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20; in i740fb_decode_var()
539 r7 |= 0x80; in i740fb_decode_var()
544 ((yres + lower - 1 + vslen) & 0x0F) & ~0x10; in i740fb_decode_var()
545 /* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */ in i740fb_decode_var()
546 par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF; in i740fb_decode_var()
548 par->crtc[VGA_CRTC_UNDERLINE] = 0x00; in i740fb_decode_var()
549 par->crtc[VGA_CRTC_MODE] = 0xC3 ; in i740fb_decode_var()
550 par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF; in i740fb_decode_var()
553 par->vss = 0x00; /* 3DA */ in i740fb_decode_var()
555 for (i = 0x00; i < 0x10; i++) in i740fb_decode_var()
557 par->atc[VGA_ATC_MODE] = 0x81; in i740fb_decode_var()
558 par->atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */ in i740fb_decode_var()
559 par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F; in i740fb_decode_var()
560 par->atc[VGA_ATC_COLOR_PAGE] = 0x00; in i740fb_decode_var()
562 par->misc = 0xC3; in i740fb_decode_var()
564 par->misc &= ~0x40; in i740fb_decode_var()
566 par->misc &= ~0x80; in i740fb_decode_var()
568 par->seq[VGA_SEQ_CLOCK_MODE] = 0x01; in i740fb_decode_var()
569 par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F; in i740fb_decode_var()
570 par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00; in i740fb_decode_var()
571 par->seq[VGA_SEQ_MEMORY_MODE] = 0x06; in i740fb_decode_var()
573 par->gdc[VGA_GFX_SR_VALUE] = 0x00; in i740fb_decode_var()
574 par->gdc[VGA_GFX_SR_ENABLE] = 0x00; in i740fb_decode_var()
575 par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00; in i740fb_decode_var()
576 par->gdc[VGA_GFX_DATA_ROTATE] = 0x00; in i740fb_decode_var()
577 par->gdc[VGA_GFX_PLANE_READ] = 0; in i740fb_decode_var()
578 par->gdc[VGA_GFX_MODE] = 0x02; in i740fb_decode_var()
579 par->gdc[VGA_GFX_MISC] = 0x05; in i740fb_decode_var()
580 par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F; in i740fb_decode_var()
581 par->gdc[VGA_GFX_BIT_MASK] = 0xFF; in i740fb_decode_var()
591 case 15: /* 0rrrrrgg gggbbbbb */ in i740fb_decode_var()
605 base &= 0xFFFFFFFE; /* ...ignore the last bit. */ in i740fb_decode_var()
617 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF; in i740fb_decode_var()
618 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8; in i740fb_decode_var()
620 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE; in i740fb_decode_var()
621 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22; in i740fb_decode_var()
639 par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6; in i740fb_decode_var()
643 /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */ in i740fb_decode_var()
644 par->atc[VGA_ATC_OVERSCAN] = 0; in i740fb_decode_var()
655 par->misc |= 0x0C; in i740fb_decode_var()
661 return 0; in i740fb_decode_var()
671 var->red.offset = var->green.offset = var->blue.offset = 0; in i740fb_check_var()
680 var->blue.offset = 0; in i740fb_check_var()
688 var->blue.offset = 0; in i740fb_check_var()
696 var->blue.offset = 0; in i740fb_check_var()
703 var->blue.offset = 0; in i740fb_check_var()
718 info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) in i740fb_check_var()
721 return 0; in i740fb_check_var()
727 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20); in vga_protect()
729 i740inb(par, 0x3DA); in vga_protect()
730 i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */ in vga_protect()
736 i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20); in vga_unprotect()
738 i740inb(par, 0x3DA); in vga_unprotect()
739 i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */ in vga_unprotect()
752 memset_io(info->screen_base, 0, info->screen_size); in i740fb_set_par()
766 par->pixelpipe_cfg0 & DAC_8_BIT, 0x80); in i740fb_set_par()
768 i740inb(par, 0x3DA); in i740fb_set_par()
769 i740outb(par, 0x3C0, 0x00); in i740fb_set_par()
772 i740outb(par, VGA_MIS_W, par->misc | 0x01); in i740fb_set_par()
775 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01); in i740fb_set_par()
778 par->seq[VGA_SEQ_CLOCK_MODE] | 0x20); in i740fb_set_par()
783 i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03); in i740fb_set_par()
785 /* deprotect CRT registers 0-7 */ in i740fb_set_par()
790 for (i = 0; i < VGA_CRT_C; i++) in i740fb_set_par()
794 for (i = 0; i < VGA_GFX_C; i++) in i740fb_set_par()
798 for (i = 0; i < VGA_ATT_C; i++) { in i740fb_set_par()
805 i740outb(par, VGA_ATT_IW, 0x20); in i740fb_set_par()
821 i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F); in i740fb_set_par()
825 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B); in i740fb_set_par()
826 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C); in i740fb_set_par()
840 i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY); in i740fb_set_par()
845 i740outb(par, VGA_PEL_MSK, 0xFF); in i740fb_set_par()
846 i740outb(par, VGA_PEL_IW, 0x00); in i740fb_set_par()
847 for (i = 0; i < 256; i++) { in i740fb_set_par()
866 return 0; in i740fb_set_par()
902 return 0; in i740fb_setcolreg()
927 base &= 0xFFFFFFFE; /* ...ignore the last bit. */ in i740fb_pan_display()
935 par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF; in i740fb_pan_display()
936 par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8; in i740fb_pan_display()
937 par->ext_start_addr_hi = (base & 0x3FC00000) >> 22; in i740fb_pan_display()
939 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE; in i740fb_pan_display()
941 i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO, base & 0x000000FF); in i740fb_pan_display()
943 (base & 0x0000FF00) >> 8); in i740fb_pan_display()
945 (base & 0x3FC00000) >> 22); in i740fb_pan_display()
947 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE); in i740fb_pan_display()
949 return 0; in i740fb_pan_display()
962 SEQ01 = 0x00; in i740fb_blank()
966 SEQ01 = 0x20; in i740fb_blank()
970 SEQ01 = 0x20; in i740fb_blank()
974 SEQ01 = 0x20; in i740fb_blank()
981 i740outb(par, SRX, 0x01); in i740fb_blank()
982 SEQ01 |= i740inb(par, SRX + 1) & ~0x20; in i740fb_blank()
983 i740outb(par, SRX, 0x01); in i740fb_blank()
990 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; in i740fb_blank()
1043 info->screen_base = pci_ioremap_wc_bar(dev, 0); in i740fb_probe()
1076 info->fix.smem_start = pci_resource_start(dev, 0); in i740fb_probe()
1080 if (i740fb_setup_ddc_bus(info) == 0) { in i740fb_probe()
1133 ret = fb_alloc_cmap(&info->cmap, 256, 0); in i740fb_probe()
1150 return 0; in i740fb_probe()
1198 if (par->ref_count == 0) { in i740fb_suspend()
1201 return 0; in i740fb_suspend()
1209 return 0; in i740fb_suspend()
1220 if (par->ref_count == 0) in i740fb_resume()
1224 fb_set_suspend(info, 0); in i740fb_resume()
1229 return 0; in i740fb_resume()
1243 #define I740_ID_PCI 0x00d1
1244 #define I740_ID_AGP 0x7800
1249 { 0 }
1267 return 0; in i740fb_setup()
1273 mtrr = simple_strtoul(opt + 5, NULL, 0); in i740fb_setup()
1278 return 0; in i740fb_setup()
1316 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");