55 	rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;  in tusb_get_revision()
57 		die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,  in tusb_get_revision()
75 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),  in tusb_print_revision()
76 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),  in tusb_print_revision()
78 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),  in tusb_print_revision()
79 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),  in tusb_print_revision()
81 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),  in tusb_print_revision()
82 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),  in tusb_print_revision()
84 		TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),  in tusb_print_revision()
85 		TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),  in tusb_print_revision()
87 		TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),  in tusb_print_revision()
106 		phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_wbus_quirk()
107 		phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_wbus_quirk()
115 			musb_readl(tbase, TUSB_PHY_OTG_CTRL),  in tusb_wbus_quirk()
116 			musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));  in tusb_wbus_quirk()
117 	} else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)  in tusb_wbus_quirk()
124 			musb_readl(tbase, TUSB_PHY_OTG_CTRL),  in tusb_wbus_quirk()
125 			musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));  in tusb_wbus_quirk()
212 			val = musb_readl(fifo, 0);  in tusb_fifo_read_unaligned()
220 		val = musb_readl(fifo, 0);  in tusb_fifo_read_unaligned()
307 					val = musb_readl(fifo, 0);  in tusb_read_fifo()
349 	reg = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_draw_power()
372 	reg = musb_readl(tbase, TUSB_PRCM_CONF);  in tusb_set_clock_source()
413 	reg = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_allow_idle()
437 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_vbus_status()
438 	prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_musb_vbus_status()
448 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_vbus_status()
568 	prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);  in tusb_musb_set_vbus()
569 	conf = musb_readl(tbase, TUSB_DEV_CONF);  in tusb_musb_set_vbus()
586 		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_vbus()
622 		musb_readl(tbase, TUSB_DEV_OTG_STAT),  in tusb_musb_set_vbus()
638 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_mode()
639 	phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_musb_set_mode()
640 	phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_musb_set_mode()
641 	dev_conf = musb_readl(tbase, TUSB_DEV_CONF);  in tusb_musb_set_mode()
673 	otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_musb_set_mode()
685 	u32		otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);  in tusb_otg_ints()
834 	int_mask = musb_readl(tbase, TUSB_INT_MASK);  in tusb_musb_interrupt()
837 	int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;  in tusb_musb_interrupt()
856 			reg = musb_readl(tbase, TUSB_SCRATCH_PAD);  in tusb_musb_interrupt()
865 		reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);  in tusb_musb_interrupt()
891 		u32	dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);  in tusb_musb_interrupt()
899 		u32	musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);  in tusb_musb_interrupt()
960 	if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)  in tusb_musb_enable()
1052 	if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=  in tusb_musb_start()
1085 	reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);  in tusb_musb_start()
1089 	reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);  in tusb_musb_start()