Lines Matching refs:MUSB_CSR0
508 musb_writew(regs, MUSB_CSR0, csr); in ep0_rxstate()
528 musb_dbg(musb, "odd; csr0 %04x", musb_readw(regs, MUSB_CSR0)); in ep0_txstate()
565 musb_writew(regs, MUSB_CSR0, csr); in ep0_txstate()
613 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY); in musb_read_setup()
614 while ((musb_readw(regs, MUSB_CSR0) in musb_read_setup()
650 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
666 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
670 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
675 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND); in musb_g_ep0_irq()
689 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
863 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
880 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL); in musb_g_ep0_irq()
964 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_queue()
975 musb_writew(regs, MUSB_CSR0, musb->ackpend); in musb_g_ep0_queue()
1026 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_halt()
1036 musb_writew(regs, MUSB_CSR0, csr); in musb_g_ep0_halt()