Lines Matching +full:generic +full:- +full:xhci
1 /* SPDX-License-Identifier: GPL-2.0 */
4 * xHCI host controller driver
19 #include <linux/io-64-nonatomic-lo-hi.h>
20 #include <linux/io-64-nonatomic-hi-lo.h>
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
24 #include "pci-quirks.h"
26 #include "xhci-port.h"
27 #include "xhci-caps.h"
32 /* xHCI PCI Configuration Registers */
35 /* Max number of USB devices for any host controller - limit in section 6.1 */
37 /* Section 5.3.3 - MaxPorts */
41 * xHCI register interface.
42 * This corresponds to the eXtensible Host Controller Interface (xHCI)
47 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
49 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
50 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
51 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
52 * @hcc_params: HCCPARAMS - Capability Parameters
53 * @db_off: DBOFF - Doorbell array offset
54 * @run_regs_off: RTSOFF - Runtime register space offset
55 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
65 __le32 hcc_params2; /* xhci 1.1 */
66 /* Reserved up to (CAPLENGTH - 0x1C) */
78 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
79 * @command: USBCMD - xHC command register
80 * @status: USBSTS - xHC status register
85 * @cmd_ring: CRP - 64-bit Command Ring Pointer
86 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
87 * @config_reg: CONFIG - Configure Register
88 * @port_status_base: PORTSCn - base address for Port Status and Control
93 * @port_power_base: PORTPMSCn - base address for
95 * @port_link_base: PORTLIn - base address for Port Link Info (current
107 /* rsvd: offset 0x20-2F */
111 /* rsvd: offset 0x3C-3FF */
118 /* registers for ports 2-255 */
122 /* USBCMD - USB command - command bitmasks */
123 /* start/stop HC execution - do not write unless HC is halted*/
125 /* Reset HC - resets internal HC state machine and all registers (except
127 * The xHCI driver must reinitialize the xHC after setting this bit.
130 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
132 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
135 /* light reset (port status stays unchanged) - reset completed when this is 0 */
140 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
142 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
143 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
145 * disabled, or powered-off state.
155 /* IMAN - Interrupt Management Register */
159 /* USBSTS - USB status - status bitmasks */
160 /* HC not running - set to 1 when run/stop bit is cleared. */
164 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
169 /* save state status - '1' means xHC is saving state */
171 /* restore state status - '1' means xHC is restoring state */
177 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
182 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
193 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
197 /* stop ring immediately - abort the currently executing command */
202 /* Command Ring pointer - bit mask for the lower 32 bits. */
205 /* CONFIG - Configure Register - config_reg bitmasks */
206 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
208 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
210 /* bit 9: Configuration Information Enable, xhci 1.1 */
212 /* bits 10:31 - reserved and should be preserved */
215 * struct xhci_intr_reg - Interrupt Register Set
216 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
218 * @irq_control: IMOD - Interrupt Moderation Register.
224 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
243 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
254 /* Counter used to count down the time to the next interrupt - HW use only */
265 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
269 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
278 * MFINDEX - current microframe number
293 * Bits 0 - 7: Endpoint target
294 * Bits 8 - 15: RsvdZ
295 * Bits 16 - 31: Stream ID
312 * @port_info: Port offset, count, and protocol-defined information.
366 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
367 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
380 /* Route String - 0:19 */
382 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
386 /* Is this LS/FS device connected through a HS hub? - bit 25 */
388 /* Set if the device is a hub - bit 26 */
390 /* Index of the last valid endpoint context in this device context - 27:31 */
393 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
398 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
409 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
411 * this low or full-speed device. '0' if attached to root hub port.
415 * The number of the downstream facing port of the high-speed hub
423 /* USB device address - assigned by the HC */
442 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
450 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
451 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
459 /* offset 0x14 - 0x1f reserved for HC internal use */
465 * Endpoint State - bits 0:2
466 * 0 - disabled
467 * 1 - running
468 * 2 - halted due to halt condition - ok to manipulate endpoint ring
469 * 3 - stopped
470 * 4 - TRB error
471 * 5-7 - reserved
479 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
481 /* Mult - Max number of burtst within an interval, in EP companion desc. */
486 /* Interval - period between requests to an endpoint - 125u increments. */
500 * Force Event - generate transfer events for all TRBs for this endpoint
515 /* bit 7 is Host Initiate Disable - for disabling stream selection */
547 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
549 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
552 * It's useful to pre-allocate these for commands that cannot fail due to
553 * out-of-memory errors, like freeing streams.
566 /* xHCI command response timeout in milliseconds */
576 /* 64-bit stream ring address, cycle state, and stream type */
578 /* offset 0x14 - 0x1f reserved for HC internal use */
582 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
615 /* Some Intel xHCI host controllers need software to keep track of the bus
618 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
622 /* ep_interval is zero-based */
624 /* mult and num_packets are one-based */
671 /* Percentage of bus bandwidth reserved for non-periodic transfers */
700 /* ---- Related to URB cancellation ---- */
702 struct xhci_hcd *xhci; member
779 * See xhci 1.1 section 4.8.3 for more details
815 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
818 /* 64-bit device addresses; we only write 32-bit addresses */
823 /* TODO: write function to set the 64-bit device DMA address */
831 /* 64-bit buffer address, or immediate data */
845 /* Completion Code - only applicable for some types of TRBs */
943 return "Stopped - Length Invalid"; in xhci_trb_comp_code_string()
945 return "Stopped - Short Packet"; in xhci_trb_comp_code_string()
966 /* 64-bit segment pointer*/
985 /* Address device - disable SetAddress */
988 /* Configure Endpoint - Deconfigure */
991 /* Stop Ring - Transfer State Preserve */
1023 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1024 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1040 /* Port ID - bits 31:24 */
1046 /* transfer_len bitmasks - bits 0:16 */
1051 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1053 /* Interrupter Target - which MSI-X vector to target the completion event at */
1056 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1060 /* Cycle bit - indicates TRB ownership by HC or HCD */
1105 struct xhci_generic_trb generic; member
1126 /* Transfer Ring No-op (not for the command ring) */
1155 /* Force Header Command - generate a transaction or link management packet */
1157 /* No-op Command - not for transfer rings */
1159 /* TRB IDs 24-31 reserved */
1173 /* Device Notification Event - device sent function wake notification */
1175 /* MFINDEX Wrap Event - microframe counter wrapped */
1177 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1179 /* Nec vendor-specific command completion event. */
1202 return "No-Op"; in xhci_trb_type_string()
1232 return "No-Op Command"; in xhci_trb_type_string()
1259 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1270 * since the command ring is 64-byte aligned.
1275 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1282 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1283 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1297 /* Max packet sized bounce buffer for td-fragmant alignment */
1330 * xHCI command default timeout value in milliseconds.
1389 unsigned int num_trbs_free; /* used only by xhci DbC */
1397 /* 64-bit event ring segment address */
1407 /* xhci->event_ring keeps track of segment dma addresses */
1455 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1477 * Intel Lynx Point LP xHCI host.
1522 /* Cached register copies of read-only HC data */
1546 /* msi-x vectors */
1588 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1591 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1594 * they see this status (any time they drop and re-acquire xhci->lock).
1598 * There are no reports of xHCI host controllers that display this issue.
1671 /* support xHCI 1.0 spec USB2 hardware LPM */
1695 /* platform-specific data -- must come last */
1699 /* Platform specific overrides to generic XHCI hc_driver ops */
1726 primary_hcd = hcd->primary_hcd; in hcd_to_xhci()
1728 return (struct xhci_hcd *) (primary_hcd->hcd_priv); in hcd_to_xhci()
1731 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) in xhci_to_hcd() argument
1733 return xhci->main_hcd; in xhci_to_hcd()
1736 static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci) in xhci_get_usb3_hcd() argument
1738 if (xhci->shared_hcd) in xhci_get_usb3_hcd()
1739 return xhci->shared_hcd; in xhci_get_usb3_hcd()
1741 if (!xhci->usb2_rhub.num_ports) in xhci_get_usb3_hcd()
1742 return xhci->main_hcd; in xhci_get_usb3_hcd()
1749 struct xhci_hcd *xhci = hcd_to_xhci(hcd); in xhci_hcd_is_usb3() local
1751 return hcd == xhci_get_usb3_hcd(xhci); in xhci_hcd_is_usb3()
1754 static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci) in xhci_has_one_roothub() argument
1756 return xhci->allow_single_roothub && in xhci_has_one_roothub()
1757 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports); in xhci_has_one_roothub()
1760 #define xhci_dbg(xhci, fmt, args...) \ argument
1761 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1762 #define xhci_err(xhci, fmt, args...) \ argument
1763 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1764 #define xhci_warn(xhci, fmt, args...) \ argument
1765 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1766 #define xhci_info(xhci, fmt, args...) \ argument
1767 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1772 * Some xHCI implementations may support 64-bit address pointers. Registers
1773 * with 64-bit address pointers should be written to with dword accesses by
1775 * xHCI implementations that do not support 64-bit address pointers will ignore
1778 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, in xhci_read_64() argument
1783 static inline void xhci_write_64(struct xhci_hcd *xhci, in xhci_write_64() argument
1789 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) in xhci_link_trb_quirk() argument
1791 return xhci->quirks & XHCI_LINK_TRB_QUIRK; in xhci_link_trb_quirk()
1794 /* xHCI debugging */
1795 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1797 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1800 /* xHCI memory management */
1801 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1802 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1803 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1804 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags…
1805 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1806 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1810 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_e…
1811 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1815 void xhci_update_bw_info(struct xhci_hcd *xhci,
1819 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1823 void xhci_slot_copy(struct xhci_hcd *xhci,
1826 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1829 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1832 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1833 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1835 int xhci_alloc_erst(struct xhci_hcd *xhci,
1841 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1842 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1845 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1849 void xhci_free_stream_info(struct xhci_hcd *xhci,
1851 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1856 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1861 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1863 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1866 void xhci_free_command(struct xhci_hcd *xhci,
1868 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
1870 void xhci_free_container_ctx(struct xhci_hcd *xhci,
1873 /* xHCI host controller glue */
1876 void xhci_quiesce(struct xhci_hcd *xhci);
1877 int xhci_halt(struct xhci_hcd *xhci);
1878 int xhci_start(struct xhci_hcd *xhci);
1879 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
1894 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
1895 int xhci_ext_cap_init(struct xhci_hcd *xhci);
1897 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1898 int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
1903 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1908 /* xHCI ring, segment, TRB, and TD functions */
1910 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1913 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1914 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1915 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1917 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1919 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1921 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1923 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1925 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1927 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1929 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1931 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1934 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1936 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1939 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1941 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
1947 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1949 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
1952 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1953 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
1957 /* xHCI roothub code */
1958 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
1960 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
1968 void xhci_hc_died(struct xhci_hcd *xhci);
1981 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1983 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1985 /* xHCI contexts */
1987 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1988 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned…
1990 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1994 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, in xhci_urb_to_transfer_ring() argument
1997 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, in xhci_urb_to_transfer_ring()
1998 xhci_get_endpoint_index(&urb->ep->desc), in xhci_urb_to_transfer_ring()
1999 urb->stream_id); in xhci_urb_to_transfer_ring()
2009 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && in xhci_urb_suitable_for_idt()
2010 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
2011 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
2012 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && in xhci_urb_suitable_for_idt()
2013 !urb->num_sgs) in xhci_urb_suitable_for_idt()
2249 "type '%s' -> raw %08x %08x %08x %08x", in xhci_decode_trb()
2304 s = "full-speed"; in xhci_decode_slot_context()
2307 s = "low-speed"; in xhci_decode_slot_context()
2310 s = "high-speed"; in xhci_decode_slot_context()
2313 s = "super-speed"; in xhci_decode_slot_context()
2316 s = "super-speed plus"; in xhci_decode_slot_context()
2321 mtt ? " multi-TT" : "", in xhci_decode_slot_context()
2378 portsc & PORT_POWER ? "Powered" : "Powered-off", in xhci_decode_portsc()
2379 portsc & PORT_CONNECT ? "Connected" : "Not-connected", in xhci_decode_portsc()
2387 ret += sprintf(str + ret, "In-Reset "); in xhci_decode_portsc()