52 #define gr_write32(x, v) (iowrite32be((v), (x)))  macro
391 	gr_write32(&ep->regs->dmaaddr, req->curr_desc->paddr);  in gr_start_dma()
395 	gr_write32(&ep->regs->dmactrl, dmactrl | GR_DMACTRL_DA);  in gr_start_dma()
426 	gr_write32(&ep->regs->dmactrl, dmactrl | GR_DMACTRL_AD);  in gr_abort_dma()
672 	gr_write32(&ep->regs->epctrl, 0);  in gr_ep_reset()
673 	gr_write32(&ep->regs->dmactrl, 0);  in gr_ep_reset()
691 	gr_write32(&dev->epo[0].regs->epctrl, epctrl | GR_EPCTRL_CS);  in gr_control_stall()
693 	gr_write32(&dev->epi[0].regs->epctrl, epctrl | GR_EPCTRL_CS);  in gr_control_stall()
731 		gr_write32(&ep->regs->epctrl, epctrl | GR_EPCTRL_EH);  in gr_ep_halt_wedge()
736 		gr_write32(&ep->regs->epctrl, epctrl & ~GR_EPCTRL_EH);  in gr_ep_halt_wedge()
764 	gr_write32(&dev->regs->control, 0);  in gr_disable_interrupts_and_pullup()
804 	gr_write32(&dev->regs->control, control);  in gr_ep0_testmode_complete()
877 	gr_write32(&dev->regs->control, control);  in gr_set_address()
1178 	gr_write32(&dev->regs->control, control);  in gr_vbus_connected()
1188 	gr_write32(&dev->regs->control, GR_CONTROL_VI);  in gr_enable_vbus_detect()
1304 		gr_write32(&ep->regs->dmactrl, ep_dmactrl | GR_DMACTRL_DA);  in gr_handle_out_ep()
1340 		gr_write32(&dev->regs->status, GR_STATUS_UR);  in gr_handle_state_changes()
1587 	gr_write32(&ep->regs->epctrl, epctrl);  in gr_ep_enable()
1589 	gr_write32(&ep->regs->dmactrl, GR_DMACTRL_IE | GR_DMACTRL_AI);  in gr_ep_enable()
1821 	gr_write32(&ep->regs->epctrl, epctrl);  in gr_fifo_flush()
1869 	gr_write32(&dev->regs->control,  in gr_wakeup()
1893 	gr_write32(&dev->regs->control, control);  in gr_pullup()
2070 	gr_write32(&dev->epo[0].regs->epctrl, epctrl_val);  in gr_udc_init()
2071 	gr_write32(&dev->epi[0].regs->epctrl, epctrl_val | GR_EPCTRL_PI);  in gr_udc_init()
2072 	gr_write32(&dev->epo[0].regs->dmactrl, dmactrl_val);  in gr_udc_init()
2073 	gr_write32(&dev->epi[0].regs->dmactrl, dmactrl_val);  in gr_udc_init()