Lines Matching refs:u32
25 u32 hcsparams; /* Host Controller Structural Parameters */
26 u32 hccparams; /* Host Controller Capability Parameters */
28 u32 dciversion; /* Device Controller Interface Version */
29 u32 dccparams; /* Device Controller Capability Parameters */
32 u32 usbcmd; /* USB Command Register */
33 u32 usbsts; /* USB Status Register */
34 u32 usbintr; /* USB Interrupt Enable Register */
35 u32 frindex; /* Frame Index Register */
37 u32 deviceaddr; /* Device Address */
38 u32 endpointlistaddr; /* Endpoint List Address Register */
40 u32 burstsize; /* Master Interface Data Burst Size Register */
41 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
43 u32 configflag; /* Configure Flag Register */
44 u32 portsc1; /* Port 1 Status and Control Register */
46 u32 otgsc; /* On-The-Go Status and Control */
47 u32 usbmode; /* USB Mode Register */
48 u32 endptsetupstat; /* Endpoint Setup Status Register */
49 u32 endpointprime; /* Endpoint Initialization Register */
50 u32 endptflush; /* Endpoint Flush Register */
51 u32 endptstatus; /* Endpoint Status Register */
52 u32 endptcomplete; /* Endpoint Complete Register */
53 u32 endptctrl[6]; /* Endpoint Control Registers */
62 u32 hcsparams; /* Host Controller Structural Parameters */
63 u32 hccparams; /* Host Controller Capability Parameters */
65 u32 dciversion; /* Device Controller Interface Version */
66 u32 dccparams; /* Device Controller Capability Parameters */
69 u32 usbcmd; /* USB Command Register */
70 u32 usbsts; /* USB Status Register */
71 u32 usbintr; /* USB Interrupt Enable Register */
72 u32 frindex; /* Frame Index Register */
74 u32 periodiclistbase; /* Periodic Frame List Base Address Register */
75 u32 asynclistaddr; /* Current Asynchronous List Address Register */
77 u32 burstsize; /* Master Interface Data Burst Size Register */
78 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
80 u32 configflag; /* Configure Flag Register */
81 u32 portsc1; /* Port 1 Status and Control Register */
83 u32 otgsc; /* On-The-Go Status and Control */
84 u32 usbmode; /* USB Mode Register */
85 u32 endptsetupstat; /* Endpoint Setup Status Register */
86 u32 endpointprime; /* Endpoint Initialization Register */
87 u32 endptflush; /* Endpoint Flush Register */
88 u32 endptstatus; /* Endpoint Status Register */
89 u32 endptcomplete; /* Endpoint Complete Register */
90 u32 endptctrl[6]; /* Endpoint Control Registers */
95 u32 snoop1;
96 u32 snoop2;
97 u32 age_cnt_thresh; /* Age Count Threshold Register */
98 u32 pri_ctrl; /* Priority Control Register */
99 u32 si_ctrl; /* System Interface Control Register */
101 u32 control; /* General Purpose Control Register */
367 u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len
369 u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */
370 u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */
371 u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15),
373 u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */
374 u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */
375 u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */
376 u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */
377 u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */
378 u32 res1;
380 u32 res2[4];
402 u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set
404 u32 size_ioc_sts; /* Total bytes (30-16), IOC (15),
406 u32 buff_ptr0; /* Buffer pointer Page 0 */
407 u32 buff_ptr1; /* Buffer pointer Page 1 */
408 u32 buff_ptr2; /* Buffer pointer Page 2 */
409 u32 buff_ptr3; /* Buffer pointer Page 3 */
410 u32 buff_ptr4; /* Buffer pointer Page 4 */
411 u32 res;
499 u32 max_pipes; /* Device max pipes */
500 u32 bus_reset; /* Device is bus resetting */
501 u32 resume_state; /* USB state to resume */
502 u32 usb_state; /* USB current state */
503 u32 ep0_state; /* Endpoint zero state */
504 u32 ep0_dir; /* Endpoint zero direction: can be