204 static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val)  in dwc3_octeon_writeq()  function
238 static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { }  in dwc3_octeon_writeq()  function
285 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
290 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
302 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
312 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
337 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
345 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
365 	dwc3_octeon_writeq(uctl_host_cfg_reg, val);  in dwc3_octeon_setup()
370 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
378 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
383 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_setup()
400 	dwc3_octeon_writeq(uctl_shim_cfg_reg, val);  in dwc3_octeon_set_endian_mode()
410 	dwc3_octeon_writeq(uctl_ctl_reg, val);  in dwc3_octeon_phy_reset()