Lines Matching full:dwc
47 * @dwc: pointer to our context structure
49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
52 struct device *dev = dwc->dev;
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
96 if (mode != dwc->dr_mode) {
101 dwc->dr_mode = mode;
107 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
111 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
112 if (enable && !dwc->dis_u3_susphy_quirk)
117 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
119 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
120 if (enable && !dwc->dis_u2_susphy_quirk)
125 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
128 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy)
133 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
140 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
143 dwc3_enable_susphy(dwc, false);
148 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
150 dwc->current_dr_role = mode;
155 struct dwc3 *dwc = work_to_dwc(work);
161 mutex_lock(&dwc->mutex);
162 spin_lock_irqsave(&dwc->lock, flags);
163 desired_dr_role = dwc->desired_dr_role;
164 spin_unlock_irqrestore(&dwc->lock, flags);
166 pm_runtime_get_sync(dwc->dev);
168 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
169 dwc3_otg_update(dwc, 0);
174 if (desired_dr_role == dwc->current_dr_role)
177 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
180 switch (dwc->current_dr_role) {
182 dwc3_host_exit(dwc);
185 dwc3_gadget_exit(dwc);
186 dwc3_event_buffers_cleanup(dwc);
189 dwc3_otg_exit(dwc);
190 spin_lock_irqsave(&dwc->lock, flags);
191 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
192 spin_unlock_irqrestore(&dwc->lock, flags);
193 dwc3_otg_update(dwc, 1);
203 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
206 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
208 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
218 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
220 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
223 spin_lock_irqsave(&dwc->lock, flags);
225 dwc3_set_prtcap(dwc, desired_dr_role, false);
227 spin_unlock_irqrestore(&dwc->lock, flags);
231 ret = dwc3_host_init(dwc);
233 dev_err(dwc->dev, "failed to initialize host\n");
235 if (dwc->usb2_phy)
236 otg_set_vbus(dwc->usb2_phy->otg, true);
237 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
238 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
239 if (dwc->dis_split_quirk) {
240 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
242 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
247 dwc3_core_soft_reset(dwc);
249 dwc3_event_buffers_setup(dwc);
251 if (dwc->usb2_phy)
252 otg_set_vbus(dwc->usb2_phy->otg, false);
253 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
254 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
256 ret = dwc3_gadget_init(dwc);
258 dev_err(dwc->dev, "failed to initialize peripheral\n");
261 dwc3_otg_init(dwc);
262 dwc3_otg_update(dwc, 0);
269 pm_runtime_mark_last_busy(dwc->dev);
270 pm_runtime_put_autosuspend(dwc->dev);
271 mutex_unlock(&dwc->mutex);
274 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
278 if (dwc->dr_mode != USB_DR_MODE_OTG)
281 spin_lock_irqsave(&dwc->lock, flags);
282 dwc->desired_dr_role = mode;
283 spin_unlock_irqrestore(&dwc->lock, flags);
285 queue_work(system_freezable_wq, &dwc->drd_work);
290 struct dwc3 *dwc = dep->dwc;
293 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
297 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
304 * @dwc: pointer to our context structure
306 int dwc3_core_soft_reset(struct dwc3 *dwc)
316 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
319 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
322 dwc3_gadget_dctl_write_safe(dwc, reg);
334 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
344 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
363 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
371 if (dwc->fladj == 0)
374 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
376 if (dft != dwc->fladj) {
378 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
379 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
389 * @dwc: Pointer to our controller context structure
391 static void dwc3_ref_clk_period(struct dwc3 *dwc)
399 if (dwc->ref_clk) {
400 rate = clk_get_rate(dwc->ref_clk);
404 } else if (dwc->ref_clk_per) {
405 period = dwc->ref_clk_per;
411 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
414 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
442 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
450 if (dwc->gfladj_refclk_lpm_sel)
453 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
458 * @dwc: Pointer to our controller context structure
461 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
464 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
469 * @dwc: Pointer to our controller context structure
475 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
480 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
484 evt->dwc = dwc;
486 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
490 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
500 * @dwc: Pointer to our controller context structure
502 static void dwc3_free_event_buffers(struct dwc3 *dwc)
506 evt = dwc->ev_buf;
508 dwc3_free_one_event_buffer(dwc, evt);
513 * @dwc: pointer to our controller context structure
516 * Returns 0 on success otherwise negative errno. In the error case, dwc
519 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
524 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
526 dwc->ev_buf = NULL;
530 evt = dwc3_alloc_one_event_buffer(dwc, length);
532 dev_err(dwc->dev, "can't allocate event buffer\n");
535 dwc->ev_buf = evt;
542 * @dwc: pointer to our controller context structure
546 int dwc3_event_buffers_setup(struct dwc3 *dwc)
551 if (!dwc->ev_buf)
554 evt = dwc->ev_buf;
556 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
558 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
560 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
564 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
565 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
569 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
574 if (!dwc->ev_buf)
580 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
584 evt = dwc->ev_buf;
588 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
589 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
590 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
594 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
595 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
598 static void dwc3_core_num_eps(struct dwc3 *dwc)
600 struct dwc3_hwparams *parms = &dwc->hwparams;
602 dwc->num_eps = DWC3_NUM_EPS(parms);
605 static void dwc3_cache_hwparams(struct dwc3 *dwc)
607 struct dwc3_hwparams *parms = &dwc->hwparams;
609 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
610 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
611 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
612 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
613 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
614 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
615 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
616 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
617 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
620 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
623 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
628 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
632 dwc->hsphy_interface &&
633 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
634 ret = dwc3_ulpi_init(dwc);
641 * @dwc: Pointer to our controller context structure
647 static int dwc3_phy_setup(struct dwc3 *dwc)
651 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
662 if (dwc->u2ss_inp3_quirk)
665 if (dwc->dis_rxdet_inp3_quirk)
668 if (dwc->req_p1p2p3_quirk)
671 if (dwc->del_p1p2p3_quirk)
674 if (dwc->del_phy_power_chg_quirk)
677 if (dwc->lfps_filter_quirk)
680 if (dwc->rx_detect_poll_quirk)
683 if (dwc->tx_de_emphasis_quirk)
684 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
686 if (dwc->dis_del_phy_power_chg_quirk)
689 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
691 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
694 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
696 if (dwc->hsphy_interface &&
697 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
700 } else if (dwc->hsphy_interface &&
701 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
703 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
715 switch (dwc->hsphy_mode) {
735 if (dwc->dis_enblslpm_quirk)
740 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
750 if (dwc->ulpi_ext_vbus_drv)
753 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
758 static int dwc3_phy_init(struct dwc3 *dwc)
762 usb_phy_init(dwc->usb2_phy);
763 usb_phy_init(dwc->usb3_phy);
765 ret = phy_init(dwc->usb2_generic_phy);
769 ret = phy_init(dwc->usb3_generic_phy);
776 phy_exit(dwc->usb2_generic_phy);
778 usb_phy_shutdown(dwc->usb3_phy);
779 usb_phy_shutdown(dwc->usb2_phy);
784 static void dwc3_phy_exit(struct dwc3 *dwc)
786 phy_exit(dwc->usb3_generic_phy);
787 phy_exit(dwc->usb2_generic_phy);
789 usb_phy_shutdown(dwc->usb3_phy);
790 usb_phy_shutdown(dwc->usb2_phy);
793 static int dwc3_phy_power_on(struct dwc3 *dwc)
797 usb_phy_set_suspend(dwc->usb2_phy, 0);
798 usb_phy_set_suspend(dwc->usb3_phy, 0);
800 ret = phy_power_on(dwc->usb2_generic_phy);
804 ret = phy_power_on(dwc->usb3_generic_phy);
825 dwc3_enable_susphy(dwc, true);
830 phy_power_off(dwc->usb2_generic_phy);
832 usb_phy_set_suspend(dwc->usb3_phy, 1);
833 usb_phy_set_suspend(dwc->usb2_phy, 1);
838 static void dwc3_phy_power_off(struct dwc3 *dwc)
840 phy_power_off(dwc->usb3_generic_phy);
841 phy_power_off(dwc->usb2_generic_phy);
843 usb_phy_set_suspend(dwc->usb3_phy, 1);
844 usb_phy_set_suspend(dwc->usb2_phy, 1);
847 static int dwc3_clk_enable(struct dwc3 *dwc)
851 ret = clk_prepare_enable(dwc->bus_clk);
855 ret = clk_prepare_enable(dwc->ref_clk);
859 ret = clk_prepare_enable(dwc->susp_clk);
866 clk_disable_unprepare(dwc->ref_clk);
868 clk_disable_unprepare(dwc->bus_clk);
872 static void dwc3_clk_disable(struct dwc3 *dwc)
874 clk_disable_unprepare(dwc->susp_clk);
875 clk_disable_unprepare(dwc->ref_clk);
876 clk_disable_unprepare(dwc->bus_clk);
879 static void dwc3_core_exit(struct dwc3 *dwc)
881 dwc3_event_buffers_cleanup(dwc);
882 dwc3_phy_power_off(dwc);
883 dwc3_phy_exit(dwc);
884 dwc3_clk_disable(dwc);
885 reset_control_assert(dwc->reset);
888 static bool dwc3_core_is_valid(struct dwc3 *dwc)
892 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
893 dwc->ip = DWC3_GSNPS_ID(reg);
897 dwc->revision = reg;
899 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
900 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
908 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
914 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
916 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
917 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
933 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
934 dwc->dr_mode == USB_DR_MODE_OTG) &&
967 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
968 dev_info(dwc->dev, "Running with FPGA optimizations\n");
969 dwc->is_fpga = true;
972 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
975 if (dwc->disable_scramble_quirk && dwc->is_fpga)
980 if (dwc->u2exit_lfps_quirk)
992 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
995 static int dwc3_core_get_phy(struct dwc3 *dwc);
996 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
999 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
1001 struct device *dev = dwc->dev;
1012 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
1087 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1090 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1095 if (!dwc->susp_clk)
1111 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1112 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1117 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1121 static void dwc3_config_threshold(struct dwc3 *dwc)
1133 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1134 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1135 rx_maxburst = dwc->rx_max_burst_prd;
1136 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1137 tx_maxburst = dwc->tx_max_burst_prd;
1140 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1149 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1153 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1162 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1166 rx_thr_num = dwc->rx_thr_num_pkt;
1167 rx_maxburst = dwc->rx_max_burst;
1168 tx_thr_num = dwc->tx_thr_num_pkt;
1169 tx_maxburst = dwc->tx_max_burst;
1173 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1182 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1186 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1195 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1199 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1208 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1212 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1221 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1228 * @dwc: Pointer to our controller context structure
1232 static int dwc3_core_init(struct dwc3 *dwc)
1238 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1244 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1246 ret = dwc3_phy_setup(dwc);
1250 if (!dwc->ulpi_ready) {
1251 ret = dwc3_core_ulpi_init(dwc);
1254 dwc3_core_soft_reset(dwc);
1259 dwc->ulpi_ready = true;
1262 if (!dwc->phys_ready) {
1263 ret = dwc3_core_get_phy(dwc);
1266 dwc->phys_ready = true;
1269 ret = dwc3_phy_init(dwc);
1273 ret = dwc3_core_soft_reset(dwc);
1277 dwc3_core_setup_global_control(dwc);
1278 dwc3_core_num_eps(dwc);
1281 dwc3_set_power_down_clk_scale(dwc);
1284 dwc3_frame_length_adjustment(dwc);
1287 dwc3_ref_clk_period(dwc);
1289 dwc3_set_incr_burst_type(dwc);
1291 ret = dwc3_phy_power_on(dwc);
1295 ret = dwc3_event_buffers_setup(dwc);
1297 dev_err(dwc->dev, "failed to setup event buffers\n");
1307 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1309 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1322 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1324 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1336 if (dwc->resume_hs_terminations) {
1337 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1339 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1343 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1361 if (dwc->dis_tx_ipgap_linecheck_quirk)
1364 if (dwc->parkmode_disable_ss_quirk)
1367 if (dwc->parkmode_disable_hs_quirk)
1371 (dwc->maximum_speed == USB_SPEED_HIGH ||
1372 dwc->maximum_speed == USB_SPEED_FULL))
1375 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1378 dwc3_config_threshold(dwc);
1383 dwc3_phy_power_off(dwc);
1385 dwc3_phy_exit(dwc);
1387 dwc3_ulpi_exit(dwc);
1392 static int dwc3_core_get_phy(struct dwc3 *dwc)
1394 struct device *dev = dwc->dev;
1399 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1400 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1402 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1403 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1406 if (IS_ERR(dwc->usb2_phy)) {
1407 ret = PTR_ERR(dwc->usb2_phy);
1409 dwc->usb2_phy = NULL;
1414 if (IS_ERR(dwc->usb3_phy)) {
1415 ret = PTR_ERR(dwc->usb3_phy);
1417 dwc->usb3_phy = NULL;
1422 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1423 if (IS_ERR(dwc->usb2_generic_phy)) {
1424 ret = PTR_ERR(dwc->usb2_generic_phy);
1426 dwc->usb2_generic_phy = NULL;
1431 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1432 if (IS_ERR(dwc->usb3_generic_phy)) {
1433 ret = PTR_ERR(dwc->usb3_generic_phy);
1435 dwc->usb3_generic_phy = NULL;
1443 static int dwc3_core_init_mode(struct dwc3 *dwc)
1445 struct device *dev = dwc->dev;
1448 switch (dwc->dr_mode) {
1450 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, false);
1452 if (dwc->usb2_phy)
1453 otg_set_vbus(dwc->usb2_phy->otg, false);
1454 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1455 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1457 ret = dwc3_gadget_init(dwc);
1462 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, false);
1464 if (dwc->usb2_phy)
1465 otg_set_vbus(dwc->usb2_phy->otg, true);
1466 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1467 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1469 ret = dwc3_host_init(dwc);
1474 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1475 ret = dwc3_drd_init(dwc);
1480 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1487 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1489 switch (dwc->dr_mode) {
1491 dwc3_gadget_exit(dwc);
1494 dwc3_host_exit(dwc);
1497 dwc3_drd_exit(dwc);
1505 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true);
1508 static void dwc3_get_properties(struct dwc3 *dwc)
1510 struct device *dev = dwc->dev;
1543 dwc->maximum_speed = usb_get_maximum_speed(dev);
1544 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1545 dwc->dr_mode = usb_get_dr_mode(dev);
1546 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1548 dwc->sysdev_is_parent = device_property_read_bool(dev,
1550 if (dwc->sysdev_is_parent)
1551 dwc->sysdev = dwc->dev->parent;
1553 dwc->sysdev = dwc->dev;
1555 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1557 dwc->has_lpm_erratum = device_property_read_bool(dev,
1561 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1565 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1567 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1569 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1571 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1589 dwc->do_fifo_resize = device_property_read_bool(dev,
1591 if (dwc->do_fifo_resize)
1595 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1597 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1599 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1601 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1603 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1605 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1607 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1609 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1611 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1613 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1615 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1617 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1619 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1621 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1623 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1625 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1627 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1629 dwc->resume_hs_terminations = device_property_read_bool(dev,
1631 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1633 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1635 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1637 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1640 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1645 &dwc->hsphy_interface);
1647 &dwc->fladj);
1649 &dwc->ref_clk_per);
1651 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1654 dwc->dis_split_quirk = device_property_read_bool(dev,
1657 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1658 dwc->tx_de_emphasis = tx_de_emphasis;
1660 dwc->hird_threshold = hird_threshold;
1662 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1663 dwc->rx_max_burst = rx_max_burst;
1665 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1666 dwc->tx_max_burst = tx_max_burst;
1668 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1669 dwc->rx_max_burst_prd = rx_max_burst_prd;
1671 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1672 dwc->tx_max_burst_prd = tx_max_burst_prd;
1674 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1678 bool dwc3_has_imod(struct dwc3 *dwc)
1685 static void dwc3_check_params(struct dwc3 *dwc)
1687 struct device *dev = dwc->dev;
1689 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1703 if (dwc3_has_imod((dwc)))
1704 dwc->imod_interval = 1;
1707 switch (dwc->maximum_speed) {
1724 dwc->maximum_speed);
1729 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1733 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1735 dwc->maximum_speed = USB_SPEED_SUPER;
1738 dwc->maximum_speed = USB_SPEED_HIGH;
1741 dwc->maximum_speed = USB_SPEED_SUPER;
1754 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1755 switch (dwc->max_ssp_rate) {
1770 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1772 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1776 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1784 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1786 struct device *dev = dwc->dev;
1834 static int dwc3_get_clocks(struct dwc3 *dwc)
1836 struct device *dev = dwc->dev;
1847 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1848 if (IS_ERR(dwc->bus_clk)) {
1849 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1853 if (dwc->bus_clk == NULL) {
1854 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1855 if (IS_ERR(dwc->bus_clk)) {
1856 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1861 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1862 if (IS_ERR(dwc->ref_clk)) {
1863 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1867 if (dwc->ref_clk == NULL) {
1868 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1869 if (IS_ERR(dwc->ref_clk)) {
1870 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1875 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1876 if (IS_ERR(dwc->susp_clk)) {
1877 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1881 if (dwc->susp_clk == NULL) {
1882 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1883 if (IS_ERR(dwc->susp_clk)) {
1884 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1892 static struct power_supply *dwc3_get_usb_power_supply(struct dwc3 *dwc)
1898 ret = device_property_read_string(dwc->dev, "usb-psy-name", &usb_psy_name);
1914 struct dwc3 *dwc;
1917 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1918 if (!dwc)
1921 dwc->dev = dev;
1929 dwc->xhci_resources[0].start = res->start;
1930 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1932 dwc->xhci_resources[0].flags = res->flags;
1933 dwc->xhci_resources[0].name = res->name;
1957 dwc->regs = regs;
1958 dwc->regs_size = resource_size(&dwc_res);
1960 dwc3_get_properties(dwc);
1962 dwc->usb_psy = dwc3_get_usb_power_supply(dwc);
1963 if (IS_ERR(dwc->usb_psy))
1964 return dev_err_probe(dev, PTR_ERR(dwc->usb_psy), "couldn't get usb power supply\n");
1966 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1967 if (IS_ERR(dwc->reset)) {
1968 ret = PTR_ERR(dwc->reset);
1972 ret = dwc3_get_clocks(dwc);
1976 ret = reset_control_deassert(dwc->reset);
1980 ret = dwc3_clk_enable(dwc);
1984 if (!dwc3_core_is_valid(dwc)) {
1985 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1990 platform_set_drvdata(pdev, dwc);
1991 dwc3_cache_hwparams(dwc);
1993 if (!dwc->sysdev_is_parent &&
1994 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1995 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
2000 spin_lock_init(&dwc->lock);
2001 mutex_init(&dwc->mutex);
2011 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
2013 dev_err(dwc->dev, "failed to allocate event buffers\n");
2018 dwc->edev = dwc3_get_extcon(dwc);
2019 if (IS_ERR(dwc->edev)) {
2020 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
2024 ret = dwc3_get_dr_mode(dwc);
2028 ret = dwc3_core_init(dwc);
2034 dwc3_check_params(dwc);
2035 dwc3_debugfs_init(dwc);
2037 ret = dwc3_core_init_mode(dwc);
2048 dwc3_debugfs_exit(dwc);
2049 dwc3_event_buffers_cleanup(dwc);
2050 dwc3_phy_power_off(dwc);
2051 dwc3_phy_exit(dwc);
2052 dwc3_ulpi_exit(dwc);
2054 dwc3_free_event_buffers(dwc);
2062 dwc3_clk_disable(dwc);
2064 reset_control_assert(dwc->reset);
2066 if (dwc->usb_psy)
2067 power_supply_put(dwc->usb_psy);
2074 struct dwc3 *dwc = platform_get_drvdata(pdev);
2078 dwc3_core_exit_mode(dwc);
2079 dwc3_debugfs_exit(dwc);
2081 dwc3_core_exit(dwc);
2082 dwc3_ulpi_exit(dwc);
2095 dwc3_free_event_buffers(dwc);
2097 if (dwc->usb_psy)
2098 power_supply_put(dwc->usb_psy);
2102 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2106 ret = reset_control_deassert(dwc->reset);
2110 ret = dwc3_clk_enable(dwc);
2114 ret = dwc3_core_init(dwc);
2121 dwc3_clk_disable(dwc);
2123 reset_control_assert(dwc->reset);
2128 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2132 if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) {
2133 dwc->susphy_state = (dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)) &
2135 (dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)) &
2141 if (!dwc->susphy_state)
2142 dwc3_enable_susphy(dwc, true);
2145 switch (dwc->current_dr_role) {
2147 if (pm_runtime_suspended(dwc->dev))
2149 dwc3_gadget_suspend(dwc);
2150 synchronize_irq(dwc->irq_gadget);
2151 dwc3_core_exit(dwc);
2154 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2155 dwc3_core_exit(dwc);
2160 if (dwc->dis_u2_susphy_quirk ||
2161 dwc->dis_enblslpm_quirk) {
2162 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2165 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2171 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2172 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2179 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2180 dwc3_gadget_suspend(dwc);
2181 synchronize_irq(dwc->irq_gadget);
2184 dwc3_otg_exit(dwc);
2185 dwc3_core_exit(dwc);
2195 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2200 switch (dwc->current_dr_role) {
2202 ret = dwc3_core_init_for_resume(dwc);
2206 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true);
2207 dwc3_gadget_resume(dwc);
2210 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2211 ret = dwc3_core_init_for_resume(dwc);
2214 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, true);
2218 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2219 if (dwc->dis_u2_susphy_quirk)
2222 if (dwc->dis_enblslpm_quirk)
2225 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2227 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2228 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2235 ret = dwc3_core_init_for_resume(dwc);
2239 dwc3_set_prtcap(dwc, dwc->current_dr_role, true);
2241 dwc3_otg_init(dwc);
2242 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2243 dwc3_otg_host_init(dwc);
2244 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2245 dwc3_gadget_resume(dwc);
2256 dwc3_enable_susphy(dwc, dwc->susphy_state);
2262 static int dwc3_runtime_checks(struct dwc3 *dwc)
2264 switch (dwc->current_dr_role) {
2266 if (dwc->connected)
2280 struct dwc3 *dwc = dev_get_drvdata(dev);
2283 if (dwc3_runtime_checks(dwc))
2286 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2295 struct dwc3 *dwc = dev_get_drvdata(dev);
2298 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2302 switch (dwc->current_dr_role) {
2304 if (dwc->pending_events) {
2305 pm_runtime_put(dwc->dev);
2306 dwc->pending_events = false;
2307 enable_irq(dwc->irq_gadget);
2323 struct dwc3 *dwc = dev_get_drvdata(dev);
2325 switch (dwc->current_dr_role) {
2327 if (dwc3_runtime_checks(dwc))
2346 struct dwc3 *dwc = dev_get_drvdata(dev);
2349 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2360 struct dwc3 *dwc = dev_get_drvdata(dev);
2365 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2378 struct dwc3 *dwc = dev_get_drvdata(dev);
2381 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2382 dwc->dis_split_quirk) {
2383 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2385 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);