Lines Matching refs:p
20 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params() local
22 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
23 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
24 p->max_packet_count = 511; in dwc2_set_bcm_params()
25 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
30 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params() local
32 p->otg_caps.hnp_support = false; in dwc2_set_his_params()
33 p->otg_caps.srp_support = false; in dwc2_set_his_params()
34 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_his_params()
35 p->host_rx_fifo_size = 512; in dwc2_set_his_params()
36 p->host_nperio_tx_fifo_size = 512; in dwc2_set_his_params()
37 p->host_perio_tx_fifo_size = 512; in dwc2_set_his_params()
38 p->max_transfer_size = 65535; in dwc2_set_his_params()
39 p->max_packet_count = 511; in dwc2_set_his_params()
40 p->host_channels = 16; in dwc2_set_his_params()
41 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_his_params()
42 p->phy_utmi_width = 8; in dwc2_set_his_params()
43 p->i2c_enable = false; in dwc2_set_his_params()
44 p->reload_ctl = false; in dwc2_set_his_params()
45 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_his_params()
47 p->change_speed_quirk = true; in dwc2_set_his_params()
48 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_his_params()
53 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_jz4775_params() local
55 p->otg_caps.hnp_support = false; in dwc2_set_jz4775_params()
56 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_jz4775_params()
57 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_jz4775_params()
58 p->phy_utmi_width = 16; in dwc2_set_jz4775_params()
59 p->activate_ingenic_overcurrent_detection = in dwc2_set_jz4775_params()
65 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_loongson_params() local
67 p->phy_utmi_width = 8; in dwc2_set_loongson_params()
68 p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL; in dwc2_set_loongson_params()
73 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x1600_params() local
75 p->otg_caps.hnp_support = false; in dwc2_set_x1600_params()
76 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x1600_params()
77 p->host_channels = 16; in dwc2_set_x1600_params()
78 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x1600_params()
79 p->phy_utmi_width = 16; in dwc2_set_x1600_params()
80 p->activate_ingenic_overcurrent_detection = in dwc2_set_x1600_params()
86 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_x2000_params() local
88 p->otg_caps.hnp_support = false; in dwc2_set_x2000_params()
89 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_x2000_params()
90 p->host_rx_fifo_size = 1024; in dwc2_set_x2000_params()
91 p->host_nperio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
92 p->host_perio_tx_fifo_size = 1024; in dwc2_set_x2000_params()
93 p->host_channels = 16; in dwc2_set_x2000_params()
94 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_x2000_params()
95 p->phy_utmi_width = 16; in dwc2_set_x2000_params()
96 p->activate_ingenic_overcurrent_detection = in dwc2_set_x2000_params()
102 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_s3c6400_params() local
104 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_s3c6400_params()
105 p->no_clock_gating = true; in dwc2_set_s3c6400_params()
106 p->phy_utmi_width = 8; in dwc2_set_s3c6400_params()
111 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_socfpga_agilex_params() local
113 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_socfpga_agilex_params()
114 p->no_clock_gating = true; in dwc2_set_socfpga_agilex_params()
119 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_rk_params() local
121 p->otg_caps.hnp_support = false; in dwc2_set_rk_params()
122 p->otg_caps.srp_support = false; in dwc2_set_rk_params()
123 p->host_rx_fifo_size = 525; in dwc2_set_rk_params()
124 p->host_nperio_tx_fifo_size = 128; in dwc2_set_rk_params()
125 p->host_perio_tx_fifo_size = 256; in dwc2_set_rk_params()
126 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_rk_params()
128 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_rk_params()
129 p->lpm = false; in dwc2_set_rk_params()
130 p->lpm_clock_gating = false; in dwc2_set_rk_params()
131 p->besl = false; in dwc2_set_rk_params()
132 p->hird_threshold_en = false; in dwc2_set_rk_params()
137 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_ltq_params() local
139 p->otg_caps.hnp_support = false; in dwc2_set_ltq_params()
140 p->otg_caps.srp_support = false; in dwc2_set_ltq_params()
141 p->host_rx_fifo_size = 288; in dwc2_set_ltq_params()
142 p->host_nperio_tx_fifo_size = 128; in dwc2_set_ltq_params()
143 p->host_perio_tx_fifo_size = 96; in dwc2_set_ltq_params()
144 p->max_transfer_size = 65535; in dwc2_set_ltq_params()
145 p->max_packet_count = 511; in dwc2_set_ltq_params()
146 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_ltq_params()
152 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_params() local
154 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_params()
155 p->otg_caps.srp_support = false; in dwc2_set_amlogic_params()
156 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_params()
157 p->host_rx_fifo_size = 512; in dwc2_set_amlogic_params()
158 p->host_nperio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
159 p->host_perio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
160 p->host_channels = 16; in dwc2_set_amlogic_params()
161 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_params()
162 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << in dwc2_set_amlogic_params()
164 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_amlogic_params()
169 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_g12a_params() local
171 p->lpm = false; in dwc2_set_amlogic_g12a_params()
172 p->lpm_clock_gating = false; in dwc2_set_amlogic_g12a_params()
173 p->besl = false; in dwc2_set_amlogic_g12a_params()
174 p->hird_threshold_en = false; in dwc2_set_amlogic_g12a_params()
179 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_a1_params() local
181 p->otg_caps.hnp_support = false; in dwc2_set_amlogic_a1_params()
182 p->otg_caps.srp_support = false; in dwc2_set_amlogic_a1_params()
183 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_a1_params()
184 p->host_rx_fifo_size = 192; in dwc2_set_amlogic_a1_params()
185 p->host_nperio_tx_fifo_size = 128; in dwc2_set_amlogic_a1_params()
186 p->host_perio_tx_fifo_size = 128; in dwc2_set_amlogic_a1_params()
187 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_a1_params()
188 p->phy_utmi_width = 8; in dwc2_set_amlogic_a1_params()
189 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amlogic_a1_params()
190 p->lpm = false; in dwc2_set_amlogic_a1_params()
191 p->lpm_clock_gating = false; in dwc2_set_amlogic_a1_params()
192 p->besl = false; in dwc2_set_amlogic_a1_params()
193 p->hird_threshold_en = false; in dwc2_set_amlogic_a1_params()
198 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amcc_params() local
200 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amcc_params()
205 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f4x9_fsotg_params() local
207 p->otg_caps.hnp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
208 p->otg_caps.srp_support = false; in dwc2_set_stm32f4x9_fsotg_params()
209 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32f4x9_fsotg_params()
210 p->host_rx_fifo_size = 128; in dwc2_set_stm32f4x9_fsotg_params()
211 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
212 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
213 p->max_packet_count = 256; in dwc2_set_stm32f4x9_fsotg_params()
214 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32f4x9_fsotg_params()
215 p->i2c_enable = false; in dwc2_set_stm32f4x9_fsotg_params()
216 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32f4x9_fsotg_params()
221 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f7_hsotg_params() local
223 p->host_rx_fifo_size = 622; in dwc2_set_stm32f7_hsotg_params()
224 p->host_nperio_tx_fifo_size = 128; in dwc2_set_stm32f7_hsotg_params()
225 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32f7_hsotg_params()
230 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_fsotg_params() local
232 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_fsotg_params()
233 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_fsotg_params()
234 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_fsotg_params()
235 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32mp15_fsotg_params()
236 p->host_rx_fifo_size = 128; in dwc2_set_stm32mp15_fsotg_params()
237 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
238 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
239 p->max_packet_count = 256; in dwc2_set_stm32mp15_fsotg_params()
240 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32mp15_fsotg_params()
241 p->i2c_enable = false; in dwc2_set_stm32mp15_fsotg_params()
242 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32mp15_fsotg_params()
243 p->activate_stm_id_vb_detection = true; in dwc2_set_stm32mp15_fsotg_params()
244 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_fsotg_params()
245 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_fsotg_params()
246 p->host_support_fs_ls_low_power = true; in dwc2_set_stm32mp15_fsotg_params()
247 p->host_ls_low_power_phy_clk = true; in dwc2_set_stm32mp15_fsotg_params()
252 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_hsotg_params() local
254 p->otg_caps.hnp_support = false; in dwc2_set_stm32mp15_hsotg_params()
255 p->otg_caps.srp_support = false; in dwc2_set_stm32mp15_hsotg_params()
256 p->otg_caps.otg_rev = 0x200; in dwc2_set_stm32mp15_hsotg_params()
257 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); in dwc2_set_stm32mp15_hsotg_params()
258 p->host_rx_fifo_size = 440; in dwc2_set_stm32mp15_hsotg_params()
259 p->host_nperio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
260 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
261 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_stm32mp15_hsotg_params()
262 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_hsotg_params()
263 p->lpm = false; in dwc2_set_stm32mp15_hsotg_params()
264 p->lpm_clock_gating = false; in dwc2_set_stm32mp15_hsotg_params()
265 p->besl = false; in dwc2_set_stm32mp15_hsotg_params()
266 p->hird_threshold_en = false; in dwc2_set_stm32mp15_hsotg_params()
412 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_tx_fifo_sizes() local
419 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); in dwc2_set_param_tx_fifo_sizes()
422 p->g_tx_fifo_size[i] = depth_average; in dwc2_set_param_tx_fifo_sizes()
441 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_lpm() local
443 p->lpm = hsotg->hw_params.lpm_mode; in dwc2_set_param_lpm()
444 if (p->lpm) { in dwc2_set_param_lpm()
445 p->lpm_clock_gating = true; in dwc2_set_param_lpm()
446 p->besl = true; in dwc2_set_param_lpm()
447 p->hird_threshold_en = true; in dwc2_set_param_lpm()
448 p->hird_threshold = 4; in dwc2_set_param_lpm()
450 p->lpm_clock_gating = false; in dwc2_set_param_lpm()
451 p->besl = false; in dwc2_set_param_lpm()
452 p->hird_threshold_en = false; in dwc2_set_param_lpm()
466 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_default_params() local
475 p->phy_ulpi_ddr = false; in dwc2_set_default_params()
476 p->phy_ulpi_ext_vbus = false; in dwc2_set_default_params()
478 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; in dwc2_set_default_params()
479 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; in dwc2_set_default_params()
480 p->i2c_enable = hw->i2c_enable; in dwc2_set_default_params()
481 p->acg_enable = hw->acg_enable; in dwc2_set_default_params()
482 p->ulpi_fs_ls = false; in dwc2_set_default_params()
483 p->ts_dline = false; in dwc2_set_default_params()
484 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); in dwc2_set_default_params()
485 p->uframe_sched = true; in dwc2_set_default_params()
486 p->external_id_pin_ctl = false; in dwc2_set_default_params()
487 p->ipg_isoc_en = false; in dwc2_set_default_params()
488 p->service_interval = false; in dwc2_set_default_params()
489 p->max_packet_count = hw->max_packet_count; in dwc2_set_default_params()
490 p->max_transfer_size = hw->max_transfer_size; in dwc2_set_default_params()
491 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_default_params()
492 p->ref_clk_per = 33333; in dwc2_set_default_params()
493 p->sof_cnt_wkup_alert = 100; in dwc2_set_default_params()
497 p->host_dma = dma_capable; in dwc2_set_default_params()
498 p->dma_desc_enable = false; in dwc2_set_default_params()
499 p->dma_desc_fs_enable = false; in dwc2_set_default_params()
500 p->host_support_fs_ls_low_power = false; in dwc2_set_default_params()
501 p->host_ls_low_power_phy_clk = false; in dwc2_set_default_params()
502 p->host_channels = hw->host_channels; in dwc2_set_default_params()
503 p->host_rx_fifo_size = hw->rx_fifo_size; in dwc2_set_default_params()
504 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; in dwc2_set_default_params()
505 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; in dwc2_set_default_params()
510 p->g_dma = dma_capable; in dwc2_set_default_params()
511 p->g_dma_desc = hw->dma_desc_enable; in dwc2_set_default_params()
522 p->g_rx_fifo_size = 2048; in dwc2_set_default_params()
523 p->g_np_tx_fifo_size = 1024; in dwc2_set_default_params()
537 struct dwc2_core_params *p = &hsotg->params; in dwc2_get_device_properties() local
543 &p->g_rx_fifo_size); in dwc2_get_device_properties()
546 &p->g_np_tx_fifo_size); in dwc2_get_device_properties()
551 memset(p->g_tx_fifo_size, 0, in dwc2_get_device_properties()
552 sizeof(p->g_tx_fifo_size)); in dwc2_get_device_properties()
555 &p->g_tx_fifo_size[1], in dwc2_get_device_properties()
559 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); in dwc2_get_device_properties()
562 p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current"); in dwc2_get_device_properties()
759 struct dwc2_core_params *p = &hsotg->params; in dwc2_check_params() local
791 CHECK_BOOL(dma_desc_enable, p->host_dma); in dwc2_check_params()
792 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); in dwc2_check_params()
794 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); in dwc2_check_params()
812 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); in dwc2_check_params()