Lines Matching +full:micro +full:- +full:frames
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd_ddma.c - DesignWare HS OTG Controller descriptor DMA routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
15 #include <linux/dma-mapping.h>
28 return frame & (FRLISTEN_64_SIZE - 1); in dwc2_frame_list_idx()
35 MAX_DMA_DESC_NUM_GENERIC) - 1); in dwc2_desclist_idx_inc()
40 return (idx - inc) & in dwc2_desclist_idx_dec()
42 MAX_DMA_DESC_NUM_GENERIC) - 1); in dwc2_desclist_idx_dec()
47 return (qh->ep_type == USB_ENDPOINT_XFER_ISOC && in dwc2_max_desc_num()
48 qh->dev_speed == USB_SPEED_HIGH) ? in dwc2_max_desc_num()
54 return qh->dev_speed == USB_SPEED_HIGH ? in dwc2_frame_incr_val()
55 (qh->host_interval + 8 - 1) / 8 : qh->host_interval; in dwc2_frame_incr_val()
63 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && in dwc2_desc_list_alloc()
64 qh->dev_speed == USB_SPEED_HIGH) in dwc2_desc_list_alloc()
65 desc_cache = hsotg->desc_hsisoc_cache; in dwc2_desc_list_alloc()
67 desc_cache = hsotg->desc_gen_cache; in dwc2_desc_list_alloc()
69 qh->desc_list_sz = sizeof(struct dwc2_dma_desc) * in dwc2_desc_list_alloc()
72 qh->desc_list = kmem_cache_zalloc(desc_cache, flags | GFP_DMA); in dwc2_desc_list_alloc()
73 if (!qh->desc_list) in dwc2_desc_list_alloc()
74 return -ENOMEM; in dwc2_desc_list_alloc()
76 qh->desc_list_dma = dma_map_single(hsotg->dev, qh->desc_list, in dwc2_desc_list_alloc()
77 qh->desc_list_sz, in dwc2_desc_list_alloc()
80 qh->n_bytes = kcalloc(dwc2_max_desc_num(qh), sizeof(u32), flags); in dwc2_desc_list_alloc()
81 if (!qh->n_bytes) { in dwc2_desc_list_alloc()
82 dma_unmap_single(hsotg->dev, qh->desc_list_dma, in dwc2_desc_list_alloc()
83 qh->desc_list_sz, in dwc2_desc_list_alloc()
85 kmem_cache_free(desc_cache, qh->desc_list); in dwc2_desc_list_alloc()
86 qh->desc_list = NULL; in dwc2_desc_list_alloc()
87 return -ENOMEM; in dwc2_desc_list_alloc()
97 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && in dwc2_desc_list_free()
98 qh->dev_speed == USB_SPEED_HIGH) in dwc2_desc_list_free()
99 desc_cache = hsotg->desc_hsisoc_cache; in dwc2_desc_list_free()
101 desc_cache = hsotg->desc_gen_cache; in dwc2_desc_list_free()
103 if (qh->desc_list) { in dwc2_desc_list_free()
104 dma_unmap_single(hsotg->dev, qh->desc_list_dma, in dwc2_desc_list_free()
105 qh->desc_list_sz, DMA_FROM_DEVICE); in dwc2_desc_list_free()
106 kmem_cache_free(desc_cache, qh->desc_list); in dwc2_desc_list_free()
107 qh->desc_list = NULL; in dwc2_desc_list_free()
110 kfree(qh->n_bytes); in dwc2_desc_list_free()
111 qh->n_bytes = NULL; in dwc2_desc_list_free()
116 if (hsotg->frame_list) in dwc2_frame_list_alloc()
119 hsotg->frame_list_sz = 4 * FRLISTEN_64_SIZE; in dwc2_frame_list_alloc()
120 hsotg->frame_list = kzalloc(hsotg->frame_list_sz, GFP_ATOMIC | GFP_DMA); in dwc2_frame_list_alloc()
121 if (!hsotg->frame_list) in dwc2_frame_list_alloc()
122 return -ENOMEM; in dwc2_frame_list_alloc()
124 hsotg->frame_list_dma = dma_map_single(hsotg->dev, hsotg->frame_list, in dwc2_frame_list_alloc()
125 hsotg->frame_list_sz, in dwc2_frame_list_alloc()
135 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_frame_list_free()
137 if (!hsotg->frame_list) { in dwc2_frame_list_free()
138 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_frame_list_free()
142 dma_unmap_single(hsotg->dev, hsotg->frame_list_dma, in dwc2_frame_list_free()
143 hsotg->frame_list_sz, DMA_FROM_DEVICE); in dwc2_frame_list_free()
145 kfree(hsotg->frame_list); in dwc2_frame_list_free()
146 hsotg->frame_list = NULL; in dwc2_frame_list_free()
148 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_frame_list_free()
156 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_per_sched_enable()
161 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_per_sched_enable()
165 dwc2_writel(hsotg, hsotg->frame_list_dma, HFLBADDR); in dwc2_per_sched_enable()
169 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); in dwc2_per_sched_enable()
172 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_per_sched_enable()
180 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_per_sched_disable()
185 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_per_sched_disable()
190 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); in dwc2_per_sched_disable()
193 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_per_sched_disable()
211 if (!qh->channel) { in dwc2_update_frame_list()
212 dev_err(hsotg->dev, "qh->channel = %p\n", qh->channel); in dwc2_update_frame_list()
216 if (!hsotg->frame_list) { in dwc2_update_frame_list()
217 dev_err(hsotg->dev, "hsotg->frame_list = %p\n", in dwc2_update_frame_list()
218 hsotg->frame_list); in dwc2_update_frame_list()
222 chan = qh->channel; in dwc2_update_frame_list()
224 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC) in dwc2_update_frame_list()
225 i = dwc2_frame_list_idx(qh->next_active_frame); in dwc2_update_frame_list()
232 hsotg->frame_list[j] |= 1 << chan->hc_num; in dwc2_update_frame_list()
234 hsotg->frame_list[j] &= ~(1 << chan->hc_num); in dwc2_update_frame_list()
235 j = (j + inc) & (FRLISTEN_64_SIZE - 1); in dwc2_update_frame_list()
242 dma_sync_single_for_device(hsotg->dev, in dwc2_update_frame_list()
243 hsotg->frame_list_dma, in dwc2_update_frame_list()
244 hsotg->frame_list_sz, in dwc2_update_frame_list()
250 chan->schinfo = 0; in dwc2_update_frame_list()
251 if (chan->speed == USB_SPEED_HIGH && qh->host_interval) { in dwc2_update_frame_list()
253 /* TODO - check this */ in dwc2_update_frame_list()
254 inc = (8 + qh->host_interval - 1) / qh->host_interval; in dwc2_update_frame_list()
256 chan->schinfo |= j; in dwc2_update_frame_list()
257 j = j << qh->host_interval; in dwc2_update_frame_list()
260 chan->schinfo = 0xff; in dwc2_update_frame_list()
267 struct dwc2_host_chan *chan = qh->channel; in dwc2_release_channel_ddma()
270 if (hsotg->params.uframe_sched) in dwc2_release_channel_ddma()
271 hsotg->available_host_channels++; in dwc2_release_channel_ddma()
273 hsotg->non_periodic_channels--; in dwc2_release_channel_ddma()
276 hsotg->available_host_channels++; in dwc2_release_channel_ddma()
283 if (chan->qh) { in dwc2_release_channel_ddma()
284 if (!list_empty(&chan->hc_list_entry)) in dwc2_release_channel_ddma()
285 list_del(&chan->hc_list_entry); in dwc2_release_channel_ddma()
287 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); in dwc2_release_channel_ddma()
288 chan->qh = NULL; in dwc2_release_channel_ddma()
291 qh->channel = NULL; in dwc2_release_channel_ddma()
292 qh->ntd = 0; in dwc2_release_channel_ddma()
294 if (qh->desc_list) in dwc2_release_channel_ddma()
295 memset(qh->desc_list, 0, sizeof(struct dwc2_dma_desc) * in dwc2_release_channel_ddma()
300 * dwc2_hcd_qh_init_ddma() - Initializes a QH structure's Descriptor DMA
317 if (qh->do_split) { in dwc2_hcd_qh_init_ddma()
318 dev_err(hsotg->dev, in dwc2_hcd_qh_init_ddma()
320 retval = -EINVAL; in dwc2_hcd_qh_init_ddma()
328 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC || in dwc2_hcd_qh_init_ddma()
329 qh->ep_type == USB_ENDPOINT_XFER_INT) { in dwc2_hcd_qh_init_ddma()
330 if (!hsotg->frame_list) { in dwc2_hcd_qh_init_ddma()
339 qh->ntd = 0; in dwc2_hcd_qh_init_ddma()
349 * dwc2_hcd_qh_free_ddma() - Frees a QH structure's Descriptor DMA related
371 spin_lock_irqsave(&hsotg->lock, flags); in dwc2_hcd_qh_free_ddma()
372 if (qh->channel) in dwc2_hcd_qh_free_ddma()
374 spin_unlock_irqrestore(&hsotg->lock, flags); in dwc2_hcd_qh_free_ddma()
376 if ((qh->ep_type == USB_ENDPOINT_XFER_ISOC || in dwc2_hcd_qh_free_ddma()
377 qh->ep_type == USB_ENDPOINT_XFER_INT) && in dwc2_hcd_qh_free_ddma()
378 (hsotg->params.uframe_sched || in dwc2_hcd_qh_free_ddma()
379 !hsotg->periodic_channels) && hsotg->frame_list) { in dwc2_hcd_qh_free_ddma()
387 if (qh->dev_speed == USB_SPEED_HIGH) in dwc2_frame_to_desc_idx()
388 /* Descriptor set (8 descriptors) index which is 8-aligned */ in dwc2_frame_to_desc_idx()
389 return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8; in dwc2_frame_to_desc_idx()
391 return frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1); in dwc2_frame_to_desc_idx()
396 * Few frames skipped to prevent race condition with HC.
403 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); in dwc2_calc_starting_frame()
424 if (qh->dev_speed == USB_SPEED_HIGH) { in dwc2_calc_starting_frame()
427 * the frame elapsed skip 2 frames otherwise just 1 frame. in dwc2_calc_starting_frame()
428 * Starting descriptor index must be 8-aligned, so if the in dwc2_calc_starting_frame()
432 if (dwc2_micro_frame_num(hsotg->frame_number) >= 5) { in dwc2_calc_starting_frame()
434 frame = dwc2_frame_num_inc(hsotg->frame_number, in dwc2_calc_starting_frame()
438 frame = dwc2_frame_num_inc(hsotg->frame_number, in dwc2_calc_starting_frame()
445 * Two frames are skipped for FS - the current and the next. in dwc2_calc_starting_frame()
450 frame = dwc2_frame_num_inc(hsotg->frame_number, 2); in dwc2_calc_starting_frame()
467 * when no more QTDs in the list (qh->ntd == 0). Thus this function is in dwc2_recalc_initial_desc_idx()
468 * called only when qh->ntd == 0 and qh->channel == 0. in dwc2_recalc_initial_desc_idx()
470 * So qh->channel != NULL branch is not used and just not removed from in dwc2_recalc_initial_desc_idx()
483 if (qh->channel) { in dwc2_recalc_initial_desc_idx()
491 dwc2_frame_list_idx(qh->next_active_frame) - in dwc2_recalc_initial_desc_idx()
495 qh->next_active_frame = dwc2_calc_starting_frame(hsotg, qh, in dwc2_recalc_initial_desc_idx()
497 fr_idx = dwc2_frame_list_idx(qh->next_active_frame); in dwc2_recalc_initial_desc_idx()
500 qh->td_first = qh->td_last = dwc2_frame_to_desc_idx(qh, fr_idx); in dwc2_recalc_initial_desc_idx()
516 struct dwc2_dma_desc *dma_desc = &qh->desc_list[idx]; in dwc2_fill_host_isoc_dma_desc()
520 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last]; in dwc2_fill_host_isoc_dma_desc()
522 if (frame_desc->length > max_xfer_size) in dwc2_fill_host_isoc_dma_desc()
523 qh->n_bytes[idx] = max_xfer_size; in dwc2_fill_host_isoc_dma_desc()
525 qh->n_bytes[idx] = frame_desc->length; in dwc2_fill_host_isoc_dma_desc()
527 dma_desc->buf = (u32)(qtd->urb->dma + frame_desc->offset); in dwc2_fill_host_isoc_dma_desc()
528 dma_desc->status = qh->n_bytes[idx] << HOST_DMA_ISOC_NBYTES_SHIFT & in dwc2_fill_host_isoc_dma_desc()
532 dma_desc->status |= HOST_DMA_A; in dwc2_fill_host_isoc_dma_desc()
534 qh->ntd++; in dwc2_fill_host_isoc_dma_desc()
535 qtd->isoc_frame_index_last++; in dwc2_fill_host_isoc_dma_desc()
539 if (qtd->isoc_frame_index_last == qtd->urb->packet_count) in dwc2_fill_host_isoc_dma_desc()
540 dma_desc->status |= HOST_DMA_IOC; in dwc2_fill_host_isoc_dma_desc()
543 dma_sync_single_for_device(hsotg->dev, in dwc2_fill_host_isoc_dma_desc()
544 qh->desc_list_dma + in dwc2_fill_host_isoc_dma_desc()
559 idx = qh->td_last; in dwc2_init_isoc_dma_desc()
560 inc = qh->host_interval; in dwc2_init_isoc_dma_desc()
561 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); in dwc2_init_isoc_dma_desc()
563 next_idx = dwc2_desclist_idx_inc(qh->td_last, inc, qh->dev_speed); in dwc2_init_isoc_dma_desc()
568 * qh->td_last to current frame number + 1. in dwc2_init_isoc_dma_desc()
574 dev_vdbg(hsotg->dev, in dwc2_init_isoc_dma_desc()
576 qh->td_last = dwc2_desclist_idx_inc(cur_idx, inc, in dwc2_init_isoc_dma_desc()
577 qh->dev_speed); in dwc2_init_isoc_dma_desc()
578 idx = qh->td_last; in dwc2_init_isoc_dma_desc()
582 if (qh->host_interval) { in dwc2_init_isoc_dma_desc()
583 ntd_max = (dwc2_max_desc_num(qh) + qh->host_interval - 1) / in dwc2_init_isoc_dma_desc()
584 qh->host_interval; in dwc2_init_isoc_dma_desc()
585 if (skip_frames && !qh->channel) in dwc2_init_isoc_dma_desc()
586 ntd_max -= skip_frames / qh->host_interval; in dwc2_init_isoc_dma_desc()
589 max_xfer_size = qh->dev_speed == USB_SPEED_HIGH ? in dwc2_init_isoc_dma_desc()
592 list_for_each_entry(qtd, &qh->qtd_list, qtd_list_entry) { in dwc2_init_isoc_dma_desc()
593 if (qtd->in_process && in dwc2_init_isoc_dma_desc()
594 qtd->isoc_frame_index_last == in dwc2_init_isoc_dma_desc()
595 qtd->urb->packet_count) in dwc2_init_isoc_dma_desc()
598 qtd->isoc_td_first = idx; in dwc2_init_isoc_dma_desc()
599 while (qh->ntd < ntd_max && qtd->isoc_frame_index_last < in dwc2_init_isoc_dma_desc()
600 qtd->urb->packet_count) { in dwc2_init_isoc_dma_desc()
603 idx = dwc2_desclist_idx_inc(idx, inc, qh->dev_speed); in dwc2_init_isoc_dma_desc()
606 qtd->isoc_td_last = idx; in dwc2_init_isoc_dma_desc()
607 qtd->in_process = 1; in dwc2_init_isoc_dma_desc()
610 qh->td_last = idx; in dwc2_init_isoc_dma_desc()
614 if (qh->ntd == ntd_max) { in dwc2_init_isoc_dma_desc()
615 idx = dwc2_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); in dwc2_init_isoc_dma_desc()
616 qh->desc_list[idx].status |= HOST_DMA_IOC; in dwc2_init_isoc_dma_desc()
617 dma_sync_single_for_device(hsotg->dev, in dwc2_init_isoc_dma_desc()
618 qh->desc_list_dma + (idx * in dwc2_init_isoc_dma_desc()
637 * function called from XferCompletion - QTDs was queued during in dwc2_init_isoc_dma_desc()
640 idx = dwc2_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), in dwc2_init_isoc_dma_desc()
641 qh->dev_speed); in dwc2_init_isoc_dma_desc()
648 idx = dwc2_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); in dwc2_init_isoc_dma_desc()
650 qh->desc_list[idx].status |= HOST_DMA_IOC; in dwc2_init_isoc_dma_desc()
651 dma_sync_single_for_device(hsotg->dev, in dwc2_init_isoc_dma_desc()
652 qh->desc_list_dma + in dwc2_init_isoc_dma_desc()
664 struct dwc2_dma_desc *dma_desc = &qh->desc_list[n_desc]; in dwc2_fill_host_dma_desc()
665 int len = chan->xfer_len; in dwc2_fill_host_dma_desc()
667 if (len > HOST_DMA_NBYTES_LIMIT - (chan->max_packet - 1)) in dwc2_fill_host_dma_desc()
668 len = HOST_DMA_NBYTES_LIMIT - (chan->max_packet - 1); in dwc2_fill_host_dma_desc()
670 if (chan->ep_is_in) { in dwc2_fill_host_dma_desc()
673 if (len > 0 && chan->max_packet) in dwc2_fill_host_dma_desc()
674 num_packets = (len + chan->max_packet - 1) in dwc2_fill_host_dma_desc()
675 / chan->max_packet; in dwc2_fill_host_dma_desc()
681 len = num_packets * chan->max_packet; in dwc2_fill_host_dma_desc()
684 dma_desc->status = len << HOST_DMA_NBYTES_SHIFT & HOST_DMA_NBYTES_MASK; in dwc2_fill_host_dma_desc()
685 qh->n_bytes[n_desc] = len; in dwc2_fill_host_dma_desc()
687 if (qh->ep_type == USB_ENDPOINT_XFER_CONTROL && in dwc2_fill_host_dma_desc()
688 qtd->control_phase == DWC2_CONTROL_SETUP) in dwc2_fill_host_dma_desc()
689 dma_desc->status |= HOST_DMA_SUP; in dwc2_fill_host_dma_desc()
691 dma_desc->buf = (u32)chan->xfer_dma; in dwc2_fill_host_dma_desc()
693 dma_sync_single_for_device(hsotg->dev, in dwc2_fill_host_dma_desc()
694 qh->desc_list_dma + in dwc2_fill_host_dma_desc()
703 if (len > chan->xfer_len) { in dwc2_fill_host_dma_desc()
704 chan->xfer_len = 0; in dwc2_fill_host_dma_desc()
706 chan->xfer_dma += len; in dwc2_fill_host_dma_desc()
707 chan->xfer_len -= len; in dwc2_fill_host_dma_desc()
715 struct dwc2_host_chan *chan = qh->channel; in dwc2_init_non_isoc_dma_desc()
718 dev_vdbg(hsotg->dev, "%s(): qh=%p dma=%08lx len=%d\n", __func__, qh, in dwc2_init_non_isoc_dma_desc()
719 (unsigned long)chan->xfer_dma, chan->xfer_len); in dwc2_init_non_isoc_dma_desc()
722 * Start with chan->xfer_dma initialized in assign_and_init_hc(), then in dwc2_init_non_isoc_dma_desc()
723 * if SG transfer consists of multiple URBs, this pointer is re-assigned in dwc2_init_non_isoc_dma_desc()
724 * to the buffer of the currently processed QTD. For non-SG request in dwc2_init_non_isoc_dma_desc()
728 list_for_each_entry(qtd, &qh->qtd_list, qtd_list_entry) { in dwc2_init_non_isoc_dma_desc()
729 dev_vdbg(hsotg->dev, "qtd=%p\n", qtd); in dwc2_init_non_isoc_dma_desc()
732 /* SG request - more than 1 QTD */ in dwc2_init_non_isoc_dma_desc()
733 chan->xfer_dma = qtd->urb->dma + in dwc2_init_non_isoc_dma_desc()
734 qtd->urb->actual_length; in dwc2_init_non_isoc_dma_desc()
735 chan->xfer_len = qtd->urb->length - in dwc2_init_non_isoc_dma_desc()
736 qtd->urb->actual_length; in dwc2_init_non_isoc_dma_desc()
737 dev_vdbg(hsotg->dev, "buf=%08lx len=%d\n", in dwc2_init_non_isoc_dma_desc()
738 (unsigned long)chan->xfer_dma, chan->xfer_len); in dwc2_init_non_isoc_dma_desc()
741 qtd->n_desc = 0; in dwc2_init_non_isoc_dma_desc()
744 qh->desc_list[n_desc - 1].status |= HOST_DMA_A; in dwc2_init_non_isoc_dma_desc()
745 dev_vdbg(hsotg->dev, in dwc2_init_non_isoc_dma_desc()
747 n_desc - 1, in dwc2_init_non_isoc_dma_desc()
748 &qh->desc_list[n_desc - 1]); in dwc2_init_non_isoc_dma_desc()
749 dma_sync_single_for_device(hsotg->dev, in dwc2_init_non_isoc_dma_desc()
750 qh->desc_list_dma + in dwc2_init_non_isoc_dma_desc()
751 ((n_desc - 1) * in dwc2_init_non_isoc_dma_desc()
757 dev_vdbg(hsotg->dev, in dwc2_init_non_isoc_dma_desc()
759 n_desc, &qh->desc_list[n_desc], in dwc2_init_non_isoc_dma_desc()
760 qh->desc_list[n_desc].buf, in dwc2_init_non_isoc_dma_desc()
761 qh->desc_list[n_desc].status); in dwc2_init_non_isoc_dma_desc()
762 qtd->n_desc++; in dwc2_init_non_isoc_dma_desc()
764 } while (chan->xfer_len > 0 && in dwc2_init_non_isoc_dma_desc()
767 dev_vdbg(hsotg->dev, "n_desc=%d\n", n_desc); in dwc2_init_non_isoc_dma_desc()
768 qtd->in_process = 1; in dwc2_init_non_isoc_dma_desc()
769 if (qh->ep_type == USB_ENDPOINT_XFER_CONTROL) in dwc2_init_non_isoc_dma_desc()
776 qh->desc_list[n_desc - 1].status |= in dwc2_init_non_isoc_dma_desc()
778 dev_vdbg(hsotg->dev, "set IOC/EOL/A bits in desc %d (%p)\n", in dwc2_init_non_isoc_dma_desc()
779 n_desc - 1, &qh->desc_list[n_desc - 1]); in dwc2_init_non_isoc_dma_desc()
780 dma_sync_single_for_device(hsotg->dev, in dwc2_init_non_isoc_dma_desc()
781 qh->desc_list_dma + (n_desc - 1) * in dwc2_init_non_isoc_dma_desc()
786 qh->desc_list[0].status |= HOST_DMA_A; in dwc2_init_non_isoc_dma_desc()
787 dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n", in dwc2_init_non_isoc_dma_desc()
788 &qh->desc_list[0]); in dwc2_init_non_isoc_dma_desc()
789 dma_sync_single_for_device(hsotg->dev, in dwc2_init_non_isoc_dma_desc()
790 qh->desc_list_dma, in dwc2_init_non_isoc_dma_desc()
794 chan->ntd = n_desc; in dwc2_init_non_isoc_dma_desc()
799 * dwc2_hcd_start_xfer_ddma() - Starts a transfer in Descriptor DMA mode
820 struct dwc2_host_chan *chan = qh->channel; in dwc2_hcd_start_xfer_ddma()
823 switch (chan->ep_type) { in dwc2_hcd_start_xfer_ddma()
835 if (!qh->ntd) in dwc2_hcd_start_xfer_ddma()
839 if (!chan->xfer_started) { in dwc2_hcd_start_xfer_ddma()
847 chan->ntd = dwc2_max_desc_num(qh); in dwc2_hcd_start_xfer_ddma()
874 if (!qtd->urb) in dwc2_cmpl_host_isoc_dma_desc()
875 return -EINVAL; in dwc2_cmpl_host_isoc_dma_desc()
877 usb_urb = qtd->urb->priv; in dwc2_cmpl_host_isoc_dma_desc()
879 dma_sync_single_for_cpu(hsotg->dev, qh->desc_list_dma + (idx * in dwc2_cmpl_host_isoc_dma_desc()
884 dma_desc = &qh->desc_list[idx]; in dwc2_cmpl_host_isoc_dma_desc()
885 frame_desc_idx = (idx - qtd->isoc_td_first) & (usb_urb->number_of_packets - 1); in dwc2_cmpl_host_isoc_dma_desc()
887 frame_desc = &qtd->urb->iso_descs[frame_desc_idx]; in dwc2_cmpl_host_isoc_dma_desc()
888 if (idx == qtd->isoc_td_first) in dwc2_cmpl_host_isoc_dma_desc()
889 usb_urb->start_frame = dwc2_hcd_get_frame_number(hsotg); in dwc2_cmpl_host_isoc_dma_desc()
890 dma_desc->buf = (u32)(qtd->urb->dma + frame_desc->offset); in dwc2_cmpl_host_isoc_dma_desc()
891 if (chan->ep_is_in) in dwc2_cmpl_host_isoc_dma_desc()
892 remain = (dma_desc->status & HOST_DMA_ISOC_NBYTES_MASK) >> in dwc2_cmpl_host_isoc_dma_desc()
895 if ((dma_desc->status & HOST_DMA_STS_MASK) == HOST_DMA_STS_PKTERR) { in dwc2_cmpl_host_isoc_dma_desc()
898 * in the scheduled micro-frame/frame, both indicated by in dwc2_cmpl_host_isoc_dma_desc()
901 qtd->urb->error_count++; in dwc2_cmpl_host_isoc_dma_desc()
902 frame_desc->actual_length = qh->n_bytes[idx] - remain; in dwc2_cmpl_host_isoc_dma_desc()
903 frame_desc->status = -EPROTO; in dwc2_cmpl_host_isoc_dma_desc()
906 frame_desc->actual_length = qh->n_bytes[idx] - remain; in dwc2_cmpl_host_isoc_dma_desc()
907 frame_desc->status = 0; in dwc2_cmpl_host_isoc_dma_desc()
910 if (++qtd->isoc_frame_index == usb_urb->number_of_packets) { in dwc2_cmpl_host_isoc_dma_desc()
912 * urb->status is not used for isoc transfers here. The in dwc2_cmpl_host_isoc_dma_desc()
924 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) in dwc2_cmpl_host_isoc_dma_desc()
925 return -1; in dwc2_cmpl_host_isoc_dma_desc()
929 qh->ntd--; in dwc2_cmpl_host_isoc_dma_desc()
932 if (dma_desc->status & HOST_DMA_IOC) in dwc2_cmpl_host_isoc_dma_desc()
948 qh = chan->qh; in dwc2_complete_isoc_xfer_ddma()
949 idx = qh->td_first; in dwc2_complete_isoc_xfer_ddma()
951 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { in dwc2_complete_isoc_xfer_ddma()
952 list_for_each_entry(qtd, &qh->qtd_list, qtd_list_entry) in dwc2_complete_isoc_xfer_ddma()
953 qtd->in_process = 0; in dwc2_complete_isoc_xfer_ddma()
962 * Complete all URBs marking all frames as failed, irrespective in dwc2_complete_isoc_xfer_ddma()
963 * whether some of the descriptors (frames) succeeded or not. in dwc2_complete_isoc_xfer_ddma()
965 * urb->status, some of class drivers might use it to stop in dwc2_complete_isoc_xfer_ddma()
969 -EIO : -EOVERFLOW; in dwc2_complete_isoc_xfer_ddma()
971 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, in dwc2_complete_isoc_xfer_ddma()
973 if (qtd->urb) { in dwc2_complete_isoc_xfer_ddma()
974 for (idx = 0; idx < qtd->urb->packet_count; in dwc2_complete_isoc_xfer_ddma()
976 frame_desc = &qtd->urb->iso_descs[idx]; in dwc2_complete_isoc_xfer_ddma()
977 frame_desc->status = err; in dwc2_complete_isoc_xfer_ddma()
989 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { in dwc2_complete_isoc_xfer_ddma()
990 if (!qtd->in_process) in dwc2_complete_isoc_xfer_ddma()
998 if (idx != qtd->isoc_td_first) { in dwc2_complete_isoc_xfer_ddma()
999 dev_vdbg(hsotg->dev, in dwc2_complete_isoc_xfer_ddma()
1001 idx, qtd->isoc_td_first); in dwc2_complete_isoc_xfer_ddma()
1002 idx = qtd->isoc_td_first; in dwc2_complete_isoc_xfer_ddma()
1013 idx = dwc2_desclist_idx_inc(idx, qh->host_interval, in dwc2_complete_isoc_xfer_ddma()
1014 chan->speed); in dwc2_complete_isoc_xfer_ddma()
1023 if (qh->host_interval >= 32) in dwc2_complete_isoc_xfer_ddma()
1026 qh->td_first = idx; in dwc2_complete_isoc_xfer_ddma()
1027 cur_idx = dwc2_frame_list_idx(hsotg->frame_number); in dwc2_complete_isoc_xfer_ddma()
1028 qtd_next = list_first_entry(&qh->qtd_list, in dwc2_complete_isoc_xfer_ddma()
1032 qtd_next->isoc_td_last)) in dwc2_complete_isoc_xfer_ddma()
1037 } while (idx != qh->td_first); in dwc2_complete_isoc_xfer_ddma()
1041 qh->td_first = idx; in dwc2_complete_isoc_xfer_ddma()
1051 struct dwc2_hcd_urb *urb = qtd->urb; in dwc2_update_non_isoc_urb_state_ddma()
1054 if (chan->ep_is_in) in dwc2_update_non_isoc_urb_state_ddma()
1055 remain = (dma_desc->status & HOST_DMA_NBYTES_MASK) >> in dwc2_update_non_isoc_urb_state_ddma()
1058 dev_vdbg(hsotg->dev, "remain=%d dwc2_urb=%p\n", remain, urb); in dwc2_update_non_isoc_urb_state_ddma()
1061 dev_err(hsotg->dev, "EIO\n"); in dwc2_update_non_isoc_urb_state_ddma()
1062 urb->status = -EIO; in dwc2_update_non_isoc_urb_state_ddma()
1066 if ((dma_desc->status & HOST_DMA_STS_MASK) == HOST_DMA_STS_PKTERR) { in dwc2_update_non_isoc_urb_state_ddma()
1069 dev_vdbg(hsotg->dev, "Stall\n"); in dwc2_update_non_isoc_urb_state_ddma()
1070 urb->status = -EPIPE; in dwc2_update_non_isoc_urb_state_ddma()
1073 dev_err(hsotg->dev, "Babble\n"); in dwc2_update_non_isoc_urb_state_ddma()
1074 urb->status = -EOVERFLOW; in dwc2_update_non_isoc_urb_state_ddma()
1077 dev_err(hsotg->dev, "XactErr\n"); in dwc2_update_non_isoc_urb_state_ddma()
1078 urb->status = -EPROTO; in dwc2_update_non_isoc_urb_state_ddma()
1081 dev_err(hsotg->dev, in dwc2_update_non_isoc_urb_state_ddma()
1089 if (dma_desc->status & HOST_DMA_A) { in dwc2_update_non_isoc_urb_state_ddma()
1090 dev_vdbg(hsotg->dev, in dwc2_update_non_isoc_urb_state_ddma()
1092 chan->hc_num); in dwc2_update_non_isoc_urb_state_ddma()
1096 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL) { in dwc2_update_non_isoc_urb_state_ddma()
1097 if (qtd->control_phase == DWC2_CONTROL_DATA) { in dwc2_update_non_isoc_urb_state_ddma()
1098 urb->actual_length += n_bytes - remain; in dwc2_update_non_isoc_urb_state_ddma()
1099 if (remain || urb->actual_length >= urb->length) { in dwc2_update_non_isoc_urb_state_ddma()
1101 * For Control Data stage do not set urb->status in dwc2_update_non_isoc_urb_state_ddma()
1107 } else if (qtd->control_phase == DWC2_CONTROL_STATUS) { in dwc2_update_non_isoc_urb_state_ddma()
1108 urb->status = 0; in dwc2_update_non_isoc_urb_state_ddma()
1114 urb->actual_length += n_bytes - remain; in dwc2_update_non_isoc_urb_state_ddma()
1115 dev_vdbg(hsotg->dev, "length=%d actual=%d\n", urb->length, in dwc2_update_non_isoc_urb_state_ddma()
1116 urb->actual_length); in dwc2_update_non_isoc_urb_state_ddma()
1117 if (remain || urb->actual_length >= urb->length) { in dwc2_update_non_isoc_urb_state_ddma()
1118 urb->status = 0; in dwc2_update_non_isoc_urb_state_ddma()
1133 struct dwc2_qh *qh = chan->qh; in dwc2_process_non_isoc_desc()
1134 struct dwc2_hcd_urb *urb = qtd->urb; in dwc2_process_non_isoc_desc()
1139 dev_vdbg(hsotg->dev, "%s()\n", __func__); in dwc2_process_non_isoc_desc()
1142 return -EINVAL; in dwc2_process_non_isoc_desc()
1144 dma_sync_single_for_cpu(hsotg->dev, in dwc2_process_non_isoc_desc()
1145 qh->desc_list_dma + (desc_num * in dwc2_process_non_isoc_desc()
1150 dma_desc = &qh->desc_list[desc_num]; in dwc2_process_non_isoc_desc()
1151 n_bytes = qh->n_bytes[desc_num]; in dwc2_process_non_isoc_desc()
1152 dev_vdbg(hsotg->dev, in dwc2_process_non_isoc_desc()
1158 if (failed || (*xfer_done && urb->status != -EINPROGRESS)) { in dwc2_process_non_isoc_desc()
1159 dwc2_host_complete(hsotg, qtd, urb->status); in dwc2_process_non_isoc_desc()
1161 dev_vdbg(hsotg->dev, "failed=%1x xfer_done=%1x\n", in dwc2_process_non_isoc_desc()
1166 if (qh->ep_type == USB_ENDPOINT_XFER_CONTROL) { in dwc2_process_non_isoc_desc()
1167 switch (qtd->control_phase) { in dwc2_process_non_isoc_desc()
1169 if (urb->length > 0) in dwc2_process_non_isoc_desc()
1170 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_process_non_isoc_desc()
1172 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
1173 dev_vdbg(hsotg->dev, in dwc2_process_non_isoc_desc()
1178 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
1179 dev_vdbg(hsotg->dev, in dwc2_process_non_isoc_desc()
1181 } else if (desc_num + 1 == qtd->n_desc) { in dwc2_process_non_isoc_desc()
1204 struct dwc2_qh *qh = chan->qh; in dwc2_complete_non_isoc_xfer_ddma()
1209 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) { in dwc2_complete_non_isoc_xfer_ddma()
1210 list_for_each_entry(qtd, &qh->qtd_list, qtd_list_entry) in dwc2_complete_non_isoc_xfer_ddma()
1211 qtd->in_process = 0; in dwc2_complete_non_isoc_xfer_ddma()
1215 list_for_each_safe(qtd_item, qtd_tmp, &qh->qtd_list) { in dwc2_complete_non_isoc_xfer_ddma()
1221 qtd_desc_count = qtd->n_desc; in dwc2_complete_non_isoc_xfer_ddma()
1236 if (qh->ep_type != USB_ENDPOINT_XFER_CONTROL) { in dwc2_complete_non_isoc_xfer_ddma()
1242 qh->data_toggle = DWC2_HC_PID_DATA0; in dwc2_complete_non_isoc_xfer_ddma()
1248 if (chan->hcint & HCINTMSK_NYET) { in dwc2_complete_non_isoc_xfer_ddma()
1254 qh->ping_state = 1; in dwc2_complete_non_isoc_xfer_ddma()
1260 * dwc2_hcd_complete_xfer_ddma() - Scans the descriptor list, updates URB's
1280 struct dwc2_qh *qh = chan->qh; in dwc2_hcd_complete_xfer_ddma()
1284 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) { in dwc2_hcd_complete_xfer_ddma()
1289 list_empty(&qh->qtd_list)) { in dwc2_hcd_complete_xfer_ddma()
1297 &qh->qtd_list, in dwc2_hcd_complete_xfer_ddma()
1300 -ECONNRESET); in dwc2_hcd_complete_xfer_ddma()
1312 list_move_tail(&qh->qh_list_entry, in dwc2_hcd_complete_xfer_ddma()
1313 &hsotg->periodic_sched_assigned); in dwc2_hcd_complete_xfer_ddma()
1318 if (!chan->halt_status) in dwc2_hcd_complete_xfer_ddma()
1335 if (!list_empty(&qh->qtd_list)) { in dwc2_hcd_complete_xfer_ddma()
1337 * Add back to inactive non-periodic schedule on normal in dwc2_hcd_complete_xfer_ddma()