Lines Matching +full:ulpi +full:- +full:link
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
21 * - no_printk: Disable tracing
22 * - pr_info: Print this info to the console
23 * - trace_printk: Print this info to trace buffer (good for verbose logging)
32 dev_name(hsotg->dev), ##__VA_ARGS__)
37 dev_name(hsotg->dev), ##__VA_ARGS__)
42 /* dwc2-hsotg declarations */
74 * struct dwc2_hsotg_ep - driver endpoint definition.
88 * @mc: Multi Count - number of transactions per microframe
94 * @send_zlp: Set if we need to send a zero-length packet.
119 * as in shared-fifo mode periodic in acts like a single-frame packet
162 * struct dwc2_hsotg_req - data transfer request
177 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
178 (_hs)->driver && (_hs)->driver->_entry) { \
179 spin_unlock(&_hs->lock); \
180 (_hs)->driver->_entry(&(_hs)->gadget); \
181 spin_lock(&_hs->lock); \
209 * struct dwc2_core_params - Parameters for configuring the core
213 * - HNP and SRP capable
214 * - SRP Only capable
215 * - No HNP/SRP capable (always available)
217 * - OTG revision number the device is compliant with, in binary-coded
222 * 0 - Slave (always available)
223 * 1 - DMA (default, if available)
228 * 0 - Address DMA
229 * 1 - Descriptor DMA (default, if available)
235 * 0 - Address DMA
236 * 1 - Descriptor DMA in FS (default, if available)
240 * 0 - High Speed
241 * (default when phy_type is UTMI+ or ULPI)
242 * 1 - Full Speed
244 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
245 * 1 - Allow dynamic FIFO sizing (default, if available)
246 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
247 * are enabled for non-periodic IN endpoints in device
249 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
254 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
259 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
278 * 0 - Full Speed Phy
279 * 1 - UTMI+ Phy
280 * 2 - ULPI Phy
283 * is applicable for a phy_type of UTMI+ or ULPI. (For a
284 * ULPI phy_type, this parameter indicates the data width
285 * between the MAC and the ULPI Wrapper.) Also, this
291 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
293 * is ULPI.
294 * 0 - single data rate ULPI interface with 8 bit wide
296 * 1 - double data rate ULPI interface with 4 bit wide
298 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
300 * 0 - Internal supply (default)
301 * 1 - External supply
305 * 0 - No (default)
306 * 1 - Yes
308 * 0 - Disable (default)
309 * 1 - Enable
311 * 0 - No
312 * 1 - Yes
313 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
314 * 0 - No (default)
315 * 1 - Yes
319 * 0 - Don't support low power mode (default)
320 * 1 - Support low power mode
325 * 0 - 48 MHz
326 * (default when phy_type is UTMI+ or ULPI)
327 * 1 - 6 MHz
330 * 0 - Allow overcurrent condition to get detected
331 * 1 - Disable overcurrent condtion to get detected
333 * 0 - No (default)
334 * 1 - Yes
336 * 0 - No (default for core < 2.92a)
337 * 1 - Yes (default for core >= 2.92a)
340 * -1 - GAHBCFG value will be set to 0x06
342 * all others - GAHBCFG value will be overridden with
352 * 0 - No (default)
353 * 1 - Yes
358 * 0 - No (default)
359 * 1 - Partial power down
360 * 2 - Hibernation
362 * 0 - No (use clock gating)
363 * 1 - Yes (avoid it)
365 * 0 - No
366 * 1 - Yes
368 * 0 - No
369 * 1 - Yes
371 * 0 - No
372 * 1 - Yes
374 * 0 - No
375 * 1 - Yes
379 * 62500 - 16MHz
380 * 58823 - 17MHz
381 * 52083 - 19.2MHz
382 * 50000 - 20MHz
383 * 41666 - 24MHz
384 * 33333 - 30MHz (default)
385 * 25000 - 40MHz
393 * 0 - Deactivate the transceiver (default)
394 * 1 - Activate the transceiver
397 * 0 - Deactivate the external level detection (default)
398 * 1 - Activate the external level detection
401 * 0 - Deactivate the overcurrent detection
402 * 1 - Activate the overcurrent detection (default)
406 * DWORDS from 16-32768 (default: 2048 if
408 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
409 * DWORDS from 16-32768 (default: 1024 if
415 * 16-32768 (default: 256, 256, 256, 256, 768,
420 * 0 - No (default)
421 * 1 - Yes
423 * 0 - No
424 * 1 - Yes
428 * value of -1 (or any other out of range value) for any parameter means
505 * struct dwc2_hw_params - Autodetected parameters.
515 * 0 - HNP- and SRP-Capable OTG (Host & Device)
516 * 1 - SRP-Capable OTG (Host & Device)
517 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
518 * 3 - SRP-Capable Device
519 * 4 - Non-OTG Device
520 * 5 - SRP-Capable Host
521 * 6 - Non-OTG Host
523 * 0 - Slave only
524 * 1 - External DMA
525 * 2 - Internal DMA
527 * the worst-case scenario of Rx followed by Rx
530 * 0 - Don't support
531 * 1 - Support
544 * Non-Periodic Request Queue Depth
546 * @hs_phy_type: High-speed PHY interface type
547 * 0 - High-speed interface not supported
548 * 1 - UTMI+
549 * 2 - ULPI
550 * 3 - UTMI+ and ULPI
551 * @fs_phy_type: Full-speed PHY interface type
552 * 0 - Full speed interface not supported
553 * 1 - Dedicated full speed interface
554 * 2 - FS pins shared with UTMI+ pins
555 * 3 - FS pins shared with ULPI pins
559 * 0 - 8 bits
560 * 1 - 16 bits
561 * 2 - 8 or 16 bits
564 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
569 * 0 - Address DMA
570 * 1 - Descriptor DMA (default, if available)
571 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
572 * 1 - Allow dynamic FIFO sizing (default, if available)
573 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
574 * are enabled for non-periodic IN endpoints in device
576 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
581 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
598 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
606 * 0 - No (default)
607 * 1 - Yes
609 * 0 - Disable
610 * 1 - Enable
611 * @lpm_mode: For enabling Link Power Management in the controller
612 * 0 - Disable
613 * 1 - Enable
614 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
620 * 0 - Disable
621 * 1 - Enable
662 * struct dwc2_gregs_backup - Holds global registers state before
696 * struct dwc2_dregs_backup - Holds device registers state before
729 * struct dwc2_hregs_backup - Holds host registers state before
785 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
786 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
820 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
840 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
855 * - USB_DR_MODE_PERIPHERAL
856 * - USB_DR_MODE_HOST
857 * - USB_DR_MODE_OTG
861 * @hcd_enabled: Host mode sub-driver initialization indicator.
862 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
863 * @ll_hw_enabled: Status of low-level hardware resources.
886 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
915 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
918 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
922 * non-periodic schedule
923 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
972 * host channel is available for non-periodic transactions.
973 * @non_periodic_channels: Number of host channels assigned to non-periodic
984 * @start_work: Delayed work for handling host A-cable connection
993 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
998 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
1008 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1009 * remote-wakeup signalling
1034 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1035 * 0 - if missed SOFs frame numbers not dumbed
1222 val = readl(hsotg->regs + offset); in dwc2_readl()
1223 if (hsotg->needs_byte_swap) in dwc2_readl()
1231 if (hsotg->needs_byte_swap) in dwc2_writel()
1232 writel(swab32(value), hsotg->regs + offset); in dwc2_writel()
1234 writel(value, hsotg->regs + offset); in dwc2_writel()
1237 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); in dwc2_writel()
1250 } while (--count); in dwc2_readl_rep()
1262 } while (--count); in dwc2_writel_rep()
1287 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; in dwc2_is_iot()
1292 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; in dwc2_is_fs_iot()
1297 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; in dwc2_is_hs_iot()
1365 * These functions can be used before the internal hsotg->hw_params
1412 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1413 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
1431 { hsotg->fifo_map = 0; } in dwc2_clear_fifo_map()
1501 { schedule_work(&hsotg->phy_reset_work); } in dwc2_host_schedule_phy_reset()