62 	u32 mem_bw;
63 	u32 cfg_bw;
103 						       u32 clk_cycles);
331 	u32 tx_fsm_val = 0;  in ufs_qcom_check_hibern8()
425 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)  in ufs_qcom_get_hs_gear()
537 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,  in ufs_qcom_cfg_timers()
538 			       u32 hs, u32 rate, bool update_link_startup_timer)  in ufs_qcom_cfg_timers()
542 	u32 core_clk_period_in_ns;  in ufs_qcom_cfg_timers()
543 	u32 tx_clk_cycles_per_us = 0;  in ufs_qcom_cfg_timers()
545 	u32 core_clk_cycles_per_us = 0;  in ufs_qcom_cfg_timers()
547 	static u32 pwm_fr_table[][2] = {  in ufs_qcom_cfg_timers()
554 	static u32 hs_fr_table_rA[][2] = {  in ufs_qcom_cfg_timers()
560 	static u32 hs_fr_table_rB[][2] = {  in ufs_qcom_cfg_timers()
787 		u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);  in ufs_qcom_dev_ref_clk_ctrl()
839 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)  in ufs_qcom_icc_set_bw()
862 	int gear = max_t(u32, p->gear_rx, p->gear_tx);  in ufs_qcom_get_bw_table()
863 	int lane = max_t(u32, p->lane_rx, p->lane_tx);  in ufs_qcom_get_bw_table()
970 	u32 pa_vs_config_reg1;  in ufs_qcom_quirk_host_pa_saveconfigtime()
995 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)  in ufs_qcom_get_ufs_hci_version()
1308 						       u32 clk_cycles)  in ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div()
1311 	u32 core_clk_ctrl_reg;  in ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div()
1354 	u32 core_clk_ctrl_reg;  in ufs_qcom_clk_scale_down_pre_change()
1464 	u32 mask = TEST_BUS_SUB_SEL_MASK;  in ufs_qcom_testbus_config()
1530 		    (u32)host->testbus.select_major << 19,  in ufs_qcom_testbus_config()
1533 		    (u32)host->testbus.select_minor << offset,  in ufs_qcom_testbus_config()
1547 	u32 reg;  in ufs_qcom_dump_dbg_regs()
1795 	u32 id = desc->msi_index;  in ufs_qcom_mcq_esi_handler()