Lines Matching +full:0 +full:x0402

15 #define UNIPRO_DBG_FORCE_DME_CTRL_STATE		0x150
20 #define PA_DBG_CLK_PERIOD	0x9514
21 #define PA_DBG_TXPHY_CFGUPDT	0x9518
22 #define PA_DBG_RXPHY_CFGUPDT	0x9519
23 #define PA_DBG_MODE		0x9529
24 #define PA_DBG_SKIP_RESET_PHY	0x9539
25 #define PA_DBG_AUTOMODE_THLD	0x9536
26 #define PA_DBG_OV_TM		0x9540
27 #define PA_DBG_SKIP_LINE_RESET	0x9541
28 #define PA_DBG_LINE_RESET_REQ	0x9543
29 #define PA_DBG_OPTION_SUITE	0x9564
30 #define PA_DBG_OPTION_SUITE_DYN	0x9565
35 #define T_DBG_SKIP_INIT_HIBERN8_EXIT	0xc001
40 #define TX_LINERESET_N_VAL	0x0277
41 #define TX_LINERESET_N(v)	(((v) >> 10) & 0xFF)
42 #define TX_LINERESET_P_VAL	0x027D
43 #define TX_LINERESET_P(v)	(((v) >> 12) & 0xFF)
44 #define TX_OV_SLEEP_CNT_TIMER	0x028E
46 #define TX_OV_SLEEP_CNT(v)	(((v) >> 5) & 0x7F)
47 #define TX_HIGH_Z_CNT_11_08	0x028C
48 #define TX_HIGH_Z_CNT_H(v)	(((v) >> 8) & 0xF)
49 #define TX_HIGH_Z_CNT_07_00	0x028D
50 #define TX_HIGH_Z_CNT_L(v)	((v) & 0xFF)
51 #define TX_BASE_NVAL_07_00	0x0293
52 #define TX_BASE_NVAL_L(v)	((v) & 0xFF)
53 #define TX_BASE_NVAL_15_08	0x0294
54 #define TX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
55 #define TX_GRAN_NVAL_07_00	0x0295
56 #define TX_GRAN_NVAL_L(v)	((v) & 0xFF)
57 #define TX_GRAN_NVAL_10_08	0x0296
58 #define TX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
60 #define VND_TX_CLK_PRD		0xAA
61 #define VND_TX_CLK_PRD_EN	0xA9
62 #define VND_TX_LINERESET_PVALUE0	0xAD
63 #define VND_TX_LINERESET_PVALUE1	0xAC
64 #define VND_TX_LINERESET_PVALUE2	0xAB
68 #define VND_RX_CLK_PRD		0x12
69 #define VND_RX_CLK_PRD_EN	0x11
70 #define VND_RX_LINERESET_VALUE0	0x1D
71 #define VND_RX_LINERESET_VALUE1	0x1C
72 #define VND_RX_LINERESET_VALUE2	0x1B
76 #define RX_FILLER_ENABLE	0x0316
78 #define RX_LINERESET_VAL	0x0317
79 #define RX_LINERESET(v)	(((v) >> 12) & 0xFF)
80 #define RX_LCC_IGNORE		0x0318
81 #define RX_SYNC_MASK_LENGTH	0x0321
82 #define RX_HIBERN8_WAIT_VAL_BIT_20_16	0x0331
83 #define RX_HIBERN8_WAIT_VAL_BIT_15_08	0x0332
84 #define RX_HIBERN8_WAIT_VAL_BIT_07_00	0x0333
85 #define RX_OV_SLEEP_CNT_TIMER	0x0340
86 #define RX_OV_SLEEP_CNT(v)	(((v) >> 6) & 0x1F)
87 #define RX_OV_STALL_CNT_TIMER	0x0341
88 #define RX_OV_STALL_CNT(v)	(((v) >> 4) & 0xFF)
89 #define RX_BASE_NVAL_07_00	0x0355
90 #define RX_BASE_NVAL_L(v)	((v) & 0xFF)
91 #define RX_BASE_NVAL_15_08	0x0354
92 #define RX_BASE_NVAL_H(v)	(((v) >> 8) & 0xFF)
93 #define RX_GRAN_NVAL_07_00	0x0353
94 #define RX_GRAN_NVAL_L(v)	((v) & 0xFF)
95 #define RX_GRAN_NVAL_10_08	0x0352
96 #define RX_GRAN_NVAL_H(v)	(((v) >> 8) & 0x3)
98 #define CMN_PWM_CLK_CTRL	0x0402
99 #define PWM_CLK_CTRL_MASK	0x3
110 #define RX_ADV_FINE_GRAN_SUP_EN	0x1
111 #define RX_ADV_FINE_GRAN_STEP_VAL	0x3
112 #define RX_ADV_MIN_ACTV_TIME_CAP	0x9
114 #define PA_GRANULARITY_VAL	0x6
115 #define PA_TACTIVATE_VAL	0x3
116 #define PA_HIBERN8TIME_VAL	0x20
218 #define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)
230 	for (i = 0; i < (ufs)->avail_ln_tx; i++)