Lines Matching refs:hba
214 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_hce_enable() local
217 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL); in exynosauto_ufs_post_hce_enable()
228 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_link() local
235 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in exynosauto_ufs_pre_link()
237 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), in exynosauto_ufs_pre_link()
239 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in exynosauto_ufs_pre_link()
241 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in exynosauto_ufs_pre_link()
243 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in exynosauto_ufs_pre_link()
245 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in exynosauto_ufs_pre_link()
248 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); in exynosauto_ufs_pre_link()
249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in exynosauto_ufs_pre_link()
250 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in exynosauto_ufs_pre_link()
254 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in exynosauto_ufs_pre_link()
257 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), in exynosauto_ufs_pre_link()
260 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), in exynosauto_ufs_pre_link()
262 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), in exynosauto_ufs_pre_link()
264 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), in exynosauto_ufs_pre_link()
268 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); in exynosauto_ufs_pre_link()
271 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in exynosauto_ufs_pre_link()
273 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); in exynosauto_ufs_pre_link()
275 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000); in exynosauto_ufs_pre_link()
283 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_pre_pwr_change() local
286 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); in exynosauto_ufs_pre_pwr_change()
287 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); in exynosauto_ufs_pre_pwr_change()
288 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); in exynosauto_ufs_pre_pwr_change()
296 struct ufs_hba *hba = ufs->hba; in exynosauto_ufs_post_pwr_change() local
299 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; in exynosauto_ufs_post_pwr_change()
302 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX); in exynosauto_ufs_post_pwr_change()
309 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_pre_link() local
313 exynos_ufs_enable_ov_tm(hba); in exynos7_ufs_pre_link()
315 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
317 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
318 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
320 exynos_ufs_disable_ov_tm(hba); in exynos7_ufs_pre_link()
323 ufshcd_dme_set(hba, in exynos7_ufs_pre_link()
325 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1); in exynos7_ufs_pre_link()
327 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12)); in exynos7_ufs_pre_link()
328 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1); in exynos7_ufs_pre_link()
329 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1); in exynos7_ufs_pre_link()
330 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1); in exynos7_ufs_pre_link()
332 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val); in exynos7_ufs_pre_link()
339 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_link() local
342 exynos_ufs_enable_ov_tm(hba); in exynos7_ufs_post_link()
344 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
345 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
346 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
349 exynos_ufs_disable_ov_tm(hba); in exynos7_ufs_post_link()
351 exynos_ufs_enable_dbg_mode(hba); in exynos7_ufs_post_link()
352 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8); in exynos7_ufs_post_link()
353 exynos_ufs_disable_dbg_mode(hba); in exynos7_ufs_post_link()
369 struct ufs_hba *hba = ufs->hba; in exynos7_ufs_post_pwr_change() local
372 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1); in exynos7_ufs_post_pwr_change()
375 exynos_ufs_enable_dbg_mode(hba); in exynos7_ufs_post_pwr_change()
376 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1); in exynos7_ufs_post_pwr_change()
377 exynos_ufs_disable_dbg_mode(hba); in exynos7_ufs_post_pwr_change()
415 struct ufs_hba *hba = ufs->hba; in exynos_ufs_get_clk_info() local
416 struct list_head *head = &hba->clk_list_head; in exynos_ufs_get_clk_info()
436 dev_err(hba->dev, "failed to get clk info\n"); in exynos_ufs_get_clk_info()
457 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
482 struct ufs_hba *hba = ufs->hba; in exynos_ufs_set_pwm_clk_div() local
485 ufshcd_dme_set(hba, in exynos_ufs_set_pwm_clk_div()
491 struct ufs_hba *hba = ufs->hba; in exynos_ufs_calc_pwm_clk_div() local
512 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx); in exynos_ufs_calc_pwm_clk_div()
513 dev_err(hba->dev, in exynos_ufs_calc_pwm_clk_div()
566 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_time_attr() local
572 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_phy_time_attr()
575 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
577 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
579 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
581 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
583 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
585 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
587 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
589 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
594 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), in exynos_ufs_config_phy_time_attr()
596 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), in exynos_ufs_config_phy_time_attr()
598 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), in exynos_ufs_config_phy_time_attr()
600 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
602 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
604 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
611 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), in exynos_ufs_config_phy_time_attr()
615 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_phy_time_attr()
620 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_phy_cap_attr() local
624 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_phy_cap_attr()
627 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
630 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
633 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
636 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
639 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
642 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
649 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
653 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
659 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
666 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
672 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
678 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
685 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_phy_cap_attr()
690 struct ufs_hba *hba = ufs->hba; in exynos_ufs_establish_connt() local
699 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE); in exynos_ufs_establish_connt()
702 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID); in exynos_ufs_establish_connt()
703 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true); in exynos_ufs_establish_connt()
704 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID); in exynos_ufs_establish_connt()
705 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID); in exynos_ufs_establish_connt()
706 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS); in exynos_ufs_establish_connt()
707 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS); in exynos_ufs_establish_connt()
708 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED); in exynos_ufs_establish_connt()
731 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_sync_pattern_mask() local
753 exynos_ufs_enable_ov_tm(hba); in exynos_ufs_config_sync_pattern_mask()
756 ufshcd_dme_set(hba, in exynos_ufs_config_sync_pattern_mask()
759 exynos_ufs_disable_ov_tm(hba); in exynos_ufs_config_sync_pattern_mask()
762 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, in exynos_ufs_pre_pwr_mode() argument
766 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_pwr_mode()
801 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); in exynos_ufs_pre_pwr_mode()
802 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); in exynos_ufs_pre_pwr_mode()
803 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); in exynos_ufs_pre_pwr_mode()
811 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba, in exynos_ufs_post_pwr_mode() argument
814 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_pwr_mode()
846 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str); in exynos_ufs_post_pwr_mode()
851 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba, in exynos_ufs_specify_nexus_t_xfer_req() argument
854 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_xfer_req()
865 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba, in exynos_ufs_specify_nexus_t_tm_req() argument
868 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_specify_nexus_t_tm_req()
889 struct ufs_hba *hba = ufs->hba; in exynos_ufs_phy_init() local
894 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES), in exynos_ufs_phy_init()
896 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), in exynos_ufs_phy_init()
906 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in exynos_ufs_phy_init()
925 struct ufs_hba *hba = ufs->hba; in exynos_ufs_config_unipro() local
927 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), in exynos_ufs_config_unipro()
929 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS), in exynos_ufs_config_unipro()
931 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), in exynos_ufs_config_unipro()
956 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on, in exynos_ufs_setup_clocks() argument
959 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_setup_clocks()
977 static int exynos_ufs_pre_link(struct ufs_hba *hba) in exynos_ufs_pre_link() argument
979 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_link()
997 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE); in exynos_ufs_pre_link()
1013 static int exynos_ufs_post_link(struct ufs_hba *hba) in exynos_ufs_post_link() argument
1015 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_link()
1025 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE); in exynos_ufs_post_link()
1026 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE); in exynos_ufs_post_link()
1030 ufshcd_dme_set(hba, in exynos_ufs_post_link()
1034 exynos_ufs_enable_dbg_mode(hba); in exynos_ufs_post_link()
1035 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
1037 exynos_ufs_disable_dbg_mode(hba); in exynos_ufs_post_link()
1040 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), in exynos_ufs_post_link()
1044 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
1050 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), in exynos_ufs_post_link()
1053 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in exynos_ufs_post_link()
1058 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0); in exynos_ufs_post_link()
1062 dev_warn(hba->dev, in exynos_ufs_post_link()
1119 static inline void exynos_ufs_priv_init(struct ufs_hba *hba, in exynos_ufs_priv_init() argument
1122 ufs->hba = hba; in exynos_ufs_priv_init()
1127 hba->priv = (void *)ufs; in exynos_ufs_priv_init()
1128 hba->quirks = ufs->drv_data->quirks; in exynos_ufs_priv_init()
1131 static int exynos_ufs_init(struct ufs_hba *hba) in exynos_ufs_init() argument
1133 struct device *dev = hba->dev; in exynos_ufs_init()
1176 exynos_ufs_priv_init(hba, ufs); in exynos_ufs_init()
1194 hba->priv = NULL; in exynos_ufs_init()
1198 static int exynos_ufs_host_reset(struct ufs_hba *hba) in exynos_ufs_host_reset() argument
1200 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_host_reset()
1214 dev_err(hba->dev, "timeout host sw-reset\n"); in exynos_ufs_host_reset()
1222 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba) in exynos_ufs_dev_hw_reset() argument
1224 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_dev_hw_reset()
1231 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter) in exynos_ufs_pre_hibern8() argument
1233 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_pre_hibern8()
1264 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter) in exynos_ufs_post_hibern8() argument
1266 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_post_hibern8()
1277 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode); in exynos_ufs_post_hibern8()
1279 dev_warn(hba->dev, "%s: power mode change\n", __func__); in exynos_ufs_post_hibern8()
1280 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; in exynos_ufs_post_hibern8()
1281 hba->pwr_info.pwr_tx = cur_mode & 0xf; in exynos_ufs_post_hibern8()
1282 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); in exynos_ufs_post_hibern8()
1295 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba, in exynos_ufs_hce_enable_notify() argument
1298 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_hce_enable_notify()
1309 hba->host->max_segment_size = SZ_4K; in exynos_ufs_hce_enable_notify()
1317 ret = exynos_ufs_host_reset(hba); in exynos_ufs_hce_enable_notify()
1320 exynos_ufs_dev_hw_reset(hba); in exynos_ufs_hce_enable_notify()
1336 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba, in exynos_ufs_link_startup_notify() argument
1343 ret = exynos_ufs_pre_link(hba); in exynos_ufs_link_startup_notify()
1346 ret = exynos_ufs_post_link(hba); in exynos_ufs_link_startup_notify()
1353 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, in exynos_ufs_pwr_change_notify() argument
1362 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params, in exynos_ufs_pwr_change_notify()
1366 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params); in exynos_ufs_pwr_change_notify()
1373 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba, in exynos_ufs_hibern8_notify() argument
1379 exynos_ufs_pre_hibern8(hba, enter); in exynos_ufs_hibern8_notify()
1382 exynos_ufs_post_hibern8(hba, enter); in exynos_ufs_hibern8_notify()
1387 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, in exynos_ufs_suspend() argument
1390 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_suspend()
1395 if (!ufshcd_is_link_active(hba)) in exynos_ufs_suspend()
1401 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) in exynos_ufs_resume() argument
1403 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_resume()
1405 if (!ufshcd_is_link_active(hba)) in exynos_ufs_resume()
1413 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba, in exynosauto_ufs_vh_link_startup_notify() argument
1417 ufshcd_set_link_active(hba); in exynosauto_ufs_vh_link_startup_notify()
1418 ufshcd_set_ufs_dev_active(hba); in exynosauto_ufs_vh_link_startup_notify()
1424 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba) in exynosauto_ufs_vh_wait_ph_ready() argument
1433 mbox = ufshcd_readl(hba, PH2VH_MBOX); in exynosauto_ufs_vh_wait_ph_ready()
1446 static int exynosauto_ufs_vh_init(struct ufs_hba *hba) in exynosauto_ufs_vh_init() argument
1448 struct device *dev = hba->dev; in exynosauto_ufs_vh_init()
1464 ret = exynosauto_ufs_vh_wait_ph_ready(hba); in exynosauto_ufs_vh_init()
1472 exynos_ufs_priv_init(hba, ufs); in exynosauto_ufs_vh_init()
1480 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_link() local
1482 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD), in fsd_ufs_pre_link()
1484 ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); in fsd_ufs_pre_link()
1485 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in fsd_ufs_pre_link()
1488 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), in fsd_ufs_pre_link()
1490 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); in fsd_ufs_pre_link()
1494 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), in fsd_ufs_pre_link()
1496 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); in fsd_ufs_pre_link()
1497 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); in fsd_ufs_pre_link()
1498 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); in fsd_ufs_pre_link()
1499 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); in fsd_ufs_pre_link()
1500 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); in fsd_ufs_pre_link()
1501 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); in fsd_ufs_pre_link()
1504 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in fsd_ufs_pre_link()
1505 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20); in fsd_ufs_pre_link()
1506 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183); in fsd_ufs_pre_link()
1507 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0); in fsd_ufs_pre_link()
1517 struct ufs_hba *hba = ufs->hba; in fsd_ufs_post_link() local
1522 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), in fsd_ufs_post_link()
1524 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), in fsd_ufs_post_link()
1526 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME), in fsd_ufs_post_link()
1530 ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), in fsd_ufs_post_link()
1532 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), max_rx_hibern8_time_cap + 1); in fsd_ufs_post_link()
1534 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x01); in fsd_ufs_post_link()
1535 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xFA); in fsd_ufs_post_link()
1536 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), 0x00); in fsd_ufs_post_link()
1538 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); in fsd_ufs_post_link()
1541 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); in fsd_ufs_post_link()
1542 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); in fsd_ufs_post_link()
1543 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); in fsd_ufs_post_link()
1544 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); in fsd_ufs_post_link()
1547 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); in fsd_ufs_post_link()
1555 struct ufs_hba *hba = ufs->hba; in fsd_ufs_pre_pwr_change() local
1557 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), 0x1); in fsd_ufs_pre_pwr_change()
1558 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), 0x1); in fsd_ufs_pre_pwr_change()
1559 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000); in fsd_ufs_pre_pwr_change()
1560 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000); in fsd_ufs_pre_pwr_change()
1561 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000); in fsd_ufs_pre_pwr_change()
1610 struct ufs_hba *hba = platform_get_drvdata(pdev); in exynos_ufs_remove() local
1611 struct exynos_ufs *ufs = ufshcd_get_variant(hba); in exynos_ufs_remove()
1614 ufshcd_remove(hba); in exynos_ufs_remove()