Lines Matching refs:SELIND_LN1_RX
158 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane1()
160 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19, in tc_dwc_g210_setup_20bit_rmmi_lane1()
162 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN1_RX), 2, in tc_dwc_g210_setup_20bit_rmmi_lane1()
164 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80, in tc_dwc_g210_setup_20bit_rmmi_lane1()
166 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03, in tc_dwc_g210_setup_20bit_rmmi_lane1()
168 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16, in tc_dwc_g210_setup_20bit_rmmi_lane1()
170 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42, in tc_dwc_g210_setup_20bit_rmmi_lane1()
172 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4, in tc_dwc_g210_setup_20bit_rmmi_lane1()
174 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane1()
176 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01, in tc_dwc_g210_setup_20bit_rmmi_lane1()
178 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28, in tc_dwc_g210_setup_20bit_rmmi_lane1()
180 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E, in tc_dwc_g210_setup_20bit_rmmi_lane1()
182 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f, in tc_dwc_g210_setup_20bit_rmmi_lane1()