396 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
398 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
403 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1326 	wr_reg16(info, TCR, value);  in set_break()
2063 	wr_reg16(info, SSR, status); /* clear pending */  in isr_serial()
2203 		wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in isr_txeom()
2204 		wr_reg16(info, TCR, val); /* clear reset bit */  in isr_txeom()
2633 			wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);  in rx_enable()
2686 			wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));  in wait_mgsl_event()
2749 			wr_reg16(info, SCR,  in wait_mgsl_event()
2785 	wr_reg16(info, TCR, val);  in set_interface()
3754 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)  in wr_reg16()  function
3803 	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));  in enable_loopback()
3842 		wr_reg16(info, BDR, (unsigned short)div);  in set_rate()
3852 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_stop()
3853 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_stop()
3858 	wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);  in rx_stop()
3873 	wr_reg16(info, SSR, IRQ_RXOVER);  in rx_start()
3877 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_start()
3878 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_start()
3885 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));  in rx_start()
3893 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));  in rx_start()
3909 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
3918 		wr_reg16(info, TCR,  in tx_start()
3939 			wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_start()
3944 			wr_reg16(info, SSR, IRQ_TXIDLE);  in tx_start()
3963 	wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in tx_stop()
3968 	wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_stop()
4049 	wr_reg16(info, TCR, val);  in async_mode()
4086 	wr_reg16(info, RCR, val);  in async_mode()
4132 	wr_reg16(info, SCR, val);  in async_mode()
4211 	wr_reg16(info, TCR, val);  in sync_mode()
4274 	wr_reg16(info, RCR, val);  in sync_mode()
4325 		wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));  in sync_mode()
4356 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);  in sync_mode()
4383 	wr_reg16(info, TCR, tcr);  in tx_set_idle()
4845 		wr_reg16(info, TIR, patterns[i]);  in register_test()
4846 		wr_reg16(info, BDR, patterns[(i+1)%count]);  in register_test()
4873 	wr_reg16(info, TCR,  in irq_test()
4877 	wr_reg16(info, TDR, 0);  in irq_test()