tty/serial/zs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
38  * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
79 #define RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
81 #define RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
82 #define RES_Tx_P	0x28	/* Reset TxINT Pending */
83 #define ERR_RES		0x30	/* Error Reset */
84 #define RES_H_IUS	0x38	/* Reset highest IUS */
86 #define RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
87 #define RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
88 #define RES_EOM_L	0xC0	/* Reset EOM latch */
110 #define ADD_SM		0x4	/* Address Search Mode (SDLC) */
112 #define ENT_HM		0x10	/* Enter Hunt Mode */
132 #define SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
133 #define EXTSYNC		0x30	/* External Sync Mode */
135 #define X1CLK		0x0	/* x1 clock mode */
136 #define X16CLK		0x40	/* x16 clock mode */
137 #define X32CLK		0x80	/* x32 clock mode */
138 #define X64CLK		0xc0	/* x64 clock mode */
144 #define SDLC_CRC	0x4	/* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
167 #define NORESET		0	/* No reset on write to R9 */
168 #define CHRB		0x40	/* Reset channel B */
169 #define CHRA		0x80	/* Reset channel A */
170 #define FHWRES		0xc0	/* Force hardware reset */
174 #define LOOPMODE	2	/* SDLC Loop mode */
178 #define NRZ		0	/* NRZ mode */
179 #define NRZI		0x20	/* NRZI mode */
184 /* Write Register 11 (Clock Mode Control) */
210 #define SEARCH		0x20	/* Enter search mode */
211 #define RMC		0x40	/* Reset missing clock */
215 #define SFMM		0xc0	/* Set FM mode */
216 #define SNRZI		0xe0	/* Set NRZI mode */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */