Lines Matching defs:sab82532_async_wr_regs
41 struct sab82532_async_wr_regs { struct
42 u8 xfifo[0x20]; /* Transmit FIFO */
43 u8 cmdr; /* Command Register */
44 u8 __pad1;
45 u8 mode;
46 u8 timr;
47 u8 xon;
48 u8 xoff;
49 u8 tcr;
50 u8 dafo;
51 u8 rfc;
52 u8 __pad2;
53 u8 xbcl; /* Transmit Byte Count Low */
54 u8 xbch; /* Transmit Byte Count High */
55 u8 ccr0;
56 u8 ccr1;
57 u8 ccr2;
58 u8 ccr3;
59 u8 tsax; /* Time-Slot Assignment Reg. Transmit */
60 u8 tsar; /* Time-Slot Assignment Reg. Receive */
61 u8 xccr; /* Transmit Channel Capacity Register */
62 u8 rccr; /* Receive Channel Capacity Register */
63 u8 bgr; /* Baud Rate Generator Register */
64 u8 tic; /* Transmit Immediate Character */
65 u8 mxn; /* Mask XON Character */
66 u8 mxf; /* Mask XOFF Character */
67 u8 iva; /* Interrupt Vector Address */
68 u8 ipc;
69 u8 imr0; /* Interrupt Mask Register 0 */
70 u8 imr1; /* Interrupt Mask Register 1 */
71 u8 pvr;
72 u8 pim; /* Port Interrupt Mask */
73 u8 pcr;
74 u8 ccr4;