Lines Matching +full:rs485 +full:- +full:rx +full:- +full:during +full:- +full:tx +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
9 * Inspired by st-asc.c from STMicroelectronics (c)
15 #include <linux/dma-direction.h>
17 #include <linux/dma-mapping.h>
36 #include "stm32-usart.h"
120 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
122 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
129 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
131 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
137 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
139 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) in stm32_usart_tx_empty()
148 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_enable()
150 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_enable()
151 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_enable()
154 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_enable()
155 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
156 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_enable()
158 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
159 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_enable()
166 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_disable()
168 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_disable()
169 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_disable()
172 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_disable()
173 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
174 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_disable()
176 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
177 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_disable()
222 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_config_rs485()
223 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_config_rs485()
227 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
229 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_config_rs485()
230 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
231 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
232 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_usart_config_rs485()
240 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_usart_config_rs485()
242 rs485conf->delay_rts_before_send, in stm32_usart_config_rs485()
243 rs485conf->delay_rts_after_send, in stm32_usart_config_rs485()
246 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) in stm32_usart_config_rs485()
251 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
252 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
254 if (!port->rs485_rx_during_tx_gpio) in stm32_usart_config_rs485()
255 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_usart_config_rs485()
258 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
260 stm32_usart_clr_bits(port, ofs->cr1, in stm32_usart_config_rs485()
264 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
278 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_init_rs485()
280 rs485conf->flags = 0; in stm32_usart_init_rs485()
281 rs485conf->delay_rts_before_send = 0; in stm32_usart_init_rs485()
282 rs485conf->delay_rts_after_send = 0; in stm32_usart_init_rs485()
284 if (!pdev->dev.of_node) in stm32_usart_init_rs485()
285 return -ENODEV; in stm32_usart_init_rs485()
292 return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false; in stm32_usart_rx_dma_started()
297 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_rx_dma_terminate()
298 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_terminate()
308 struct uart_port *port = &stm32_port->port; in stm32_usart_dma_pause_resume()
313 return -EPERM; in stm32_usart_dma_pause_resume()
315 dma_status = dmaengine_tx_status(chan, chan->cookie, NULL); in stm32_usart_dma_pause_resume()
317 return -EAGAIN; in stm32_usart_dma_pause_resume()
321 dev_err(port->dev, "DMA failed with error code: %d\n", ret); in stm32_usart_dma_pause_resume()
329 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, in stm32_usart_rx_dma_pause()
337 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, in stm32_usart_rx_dma_resume()
347 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_pending_rx_pio()
349 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_pending_rx_pio()
356 /* Handle only RX data errors when using DMA */ in stm32_usart_pending_rx_pio()
367 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_get_char_pio()
370 c = readl_relaxed(port->membase + ofs->rdr); in stm32_usart_get_char_pio()
372 c &= stm32_port->rdr_mask; in stm32_usart_get_char_pio()
380 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars_pio()
394 * and clear status bits of the next rx data. in stm32_usart_receive_chars_pio()
398 * cleared by the sequence [read SR - read DR]. in stm32_usart_receive_chars_pio()
400 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_usart_receive_chars_pio()
402 port->membase + ofs->icr); in stm32_usart_receive_chars_pio()
405 port->icount.rx++; in stm32_usart_receive_chars_pio()
409 port->icount.overrun++; in stm32_usart_receive_chars_pio()
411 port->icount.parity++; in stm32_usart_receive_chars_pio()
415 port->icount.brk++; in stm32_usart_receive_chars_pio()
419 port->icount.frame++; in stm32_usart_receive_chars_pio()
423 sr &= port->read_status_mask; in stm32_usart_receive_chars_pio()
446 struct tty_port *ttyport = &stm32_port->port.state->port; in stm32_usart_push_buffer_dma()
450 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); in stm32_usart_push_buffer_dma()
457 if (!(stm32_port->rdr_mask == (BIT(8) - 1))) in stm32_usart_push_buffer_dma()
459 *(dma_start + i) &= stm32_port->rdr_mask; in stm32_usart_push_buffer_dma()
462 port->icount.rx += dma_count; in stm32_usart_push_buffer_dma()
464 port->icount.buf_overrun++; in stm32_usart_push_buffer_dma()
465 stm32_port->last_res -= dma_count; in stm32_usart_push_buffer_dma()
466 if (stm32_port->last_res == 0) in stm32_usart_push_buffer_dma()
467 stm32_port->last_res = RX_BUF_L; in stm32_usart_push_buffer_dma()
476 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { in stm32_usart_receive_chars_dma()
478 dma_size = stm32_port->last_res; in stm32_usart_receive_chars_dma()
483 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; in stm32_usart_receive_chars_dma()
493 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars()
499 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_receive_chars()
500 stm32_port->rx_ch->cookie, in stm32_usart_receive_chars()
501 &stm32_port->rx_dma_state); in stm32_usart_receive_chars()
506 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_receive_chars()
509 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
515 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
518 /* Disable RX DMA */ in stm32_usart_receive_chars()
521 dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); in stm32_usart_receive_chars()
534 struct tty_port *tport = &port->state->port; in stm32_usart_rx_dma_complete()
538 spin_lock_irqsave(&port->lock, flags); in stm32_usart_rx_dma_complete()
552 if (stm32_port->throttled) in stm32_usart_rx_dma_start_or_resume()
555 if (stm32_port->rx_dma_busy) { in stm32_usart_rx_dma_start_or_resume()
556 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_rx_dma_start_or_resume()
557 stm32_port->rx_ch->cookie, in stm32_usart_rx_dma_start_or_resume()
565 dev_err(port->dev, "DMA failed : status error.\n"); in stm32_usart_rx_dma_start_or_resume()
569 stm32_port->rx_dma_busy = true; in stm32_usart_rx_dma_start_or_resume()
571 stm32_port->last_res = RX_BUF_L; in stm32_usart_rx_dma_start_or_resume()
573 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, in stm32_usart_rx_dma_start_or_resume()
574 stm32_port->rx_dma_buf, in stm32_usart_rx_dma_start_or_resume()
579 dev_err(port->dev, "rx dma prep cyclic failed\n"); in stm32_usart_rx_dma_start_or_resume()
580 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_start_or_resume()
581 return -ENODEV; in stm32_usart_rx_dma_start_or_resume()
584 desc->callback = stm32_usart_rx_dma_complete; in stm32_usart_rx_dma_start_or_resume()
585 desc->callback_param = port; in stm32_usart_rx_dma_start_or_resume()
590 dmaengine_terminate_sync(stm32_port->rx_ch); in stm32_usart_rx_dma_start_or_resume()
591 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_start_or_resume()
596 dma_async_issue_pending(stm32_port->rx_ch); in stm32_usart_rx_dma_start_or_resume()
603 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_tx_dma_terminate()
604 stm32_port->tx_dma_busy = false; in stm32_usart_tx_dma_terminate()
616 return stm32_port->tx_dma_busy; in stm32_usart_tx_dma_started()
621 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, in stm32_usart_tx_dma_pause()
629 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, in stm32_usart_tx_dma_resume()
644 spin_lock_irqsave(&port->lock, flags); in stm32_usart_tx_dma_complete()
646 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_tx_dma_complete()
652 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_enable()
655 * Enables TX FIFO threashold irq when FIFO is enabled, in stm32_usart_tx_interrupt_enable()
656 * or TX empty irq when FIFO is disabled in stm32_usart_tx_interrupt_enable()
658 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_enable()
659 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
661 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_enable()
667 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_enable()
669 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_enable()
675 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_disable()
677 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_disable()
678 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
680 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_disable()
686 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_disable()
688 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_disable()
694 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars_pio()
695 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_pio()
699 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_transmit_chars_pio()
701 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_usart_transmit_chars_pio()
715 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_dma()
722 if (ret < 0 && ret != -EAGAIN) in stm32_usart_transmit_chars_dma()
732 if (xmit->tail < xmit->head) { in stm32_usart_transmit_chars_dma()
733 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_usart_transmit_chars_dma()
735 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_usart_transmit_chars_dma()
740 two = count - one; in stm32_usart_transmit_chars_dma()
742 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_usart_transmit_chars_dma()
744 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_usart_transmit_chars_dma()
747 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_usart_transmit_chars_dma()
748 stm32port->tx_dma_buf, in stm32_usart_transmit_chars_dma()
762 stm32port->tx_dma_busy = true; in stm32_usart_transmit_chars_dma()
764 desc->callback = stm32_usart_tx_dma_complete; in stm32_usart_transmit_chars_dma()
765 desc->callback_param = port; in stm32_usart_transmit_chars_dma()
767 /* Push current DMA TX transaction in the pending queue */ in stm32_usart_transmit_chars_dma()
771 dev_err(port->dev, "DMA failed with error code: %d\n", ret); in stm32_usart_transmit_chars_dma()
776 /* Issue pending DMA TX requests */ in stm32_usart_transmit_chars_dma()
777 dma_async_issue_pending(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
790 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars()
791 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars()
795 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
796 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_transmit_chars()
797 (port->x_char || in stm32_usart_transmit_chars()
803 if (port->x_char) { in stm32_usart_transmit_chars()
809 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_transmit_chars()
814 dev_warn(port->dev, "1 character may be erased\n"); in stm32_usart_transmit_chars()
816 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_usart_transmit_chars()
817 port->x_char = 0; in stm32_usart_transmit_chars()
818 port->icount.tx++; in stm32_usart_transmit_chars()
830 if (ofs->icr == UNDEF_REG) in stm32_usart_transmit_chars()
831 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_usart_transmit_chars()
833 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_usart_transmit_chars()
835 if (stm32_port->tx_ch) in stm32_usart_transmit_chars()
845 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
846 port->rs485.flags & SER_RS485_ENABLED) { in stm32_usart_transmit_chars()
855 struct tty_port *tport = &port->state->port; in stm32_usart_interrupt()
857 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_interrupt()
862 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_interrupt()
864 if (!stm32_port->hw_flow_control && in stm32_usart_interrupt()
865 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_interrupt()
872 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
874 port->membase + ofs->icr); in stm32_usart_interrupt()
878 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
881 port->membase + ofs->icr); in stm32_usart_interrupt()
882 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
883 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_usart_interrupt()
884 pm_wakeup_event(tport->tty->dev, 0); in stm32_usart_interrupt()
889 * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request in stm32_usart_interrupt()
890 * line has been masked by HW and rx data are stacking in FIFO. in stm32_usart_interrupt()
892 if (!stm32_port->throttled) { in stm32_usart_interrupt()
895 spin_lock(&port->lock); in stm32_usart_interrupt()
904 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { in stm32_usart_interrupt()
905 spin_lock(&port->lock); in stm32_usart_interrupt()
907 spin_unlock(&port->lock); in stm32_usart_interrupt()
911 /* Receiver timeout irq for DMA RX */ in stm32_usart_interrupt()
912 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) { in stm32_usart_interrupt()
913 spin_lock(&port->lock); in stm32_usart_interrupt()
927 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_mctrl()
929 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_usart_set_mctrl()
930 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
932 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
934 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_usart_set_mctrl()
945 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_usart_get_mctrl()
950 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_usart_enable_ms()
955 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_usart_disable_ms()
974 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_start_tx()
976 if (uart_circ_empty(xmit) && !port->x_char) { in stm32_usart_start_tx()
991 if (stm32_port->tx_ch) in stm32_usart_flush_buffer()
999 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_throttle()
1002 spin_lock_irqsave(&port->lock, flags); in stm32_usart_throttle()
1005 * Pause DMA transfer, so the RX data gets queued into the FIFO. in stm32_usart_throttle()
1006 * Hardware flow control is triggered when RX FIFO is full. in stm32_usart_throttle()
1010 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_throttle()
1011 if (stm32_port->cr3_irq) in stm32_usart_throttle()
1012 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
1014 stm32_port->throttled = true; in stm32_usart_throttle()
1015 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_throttle()
1022 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_unthrottle()
1025 spin_lock_irqsave(&port->lock, flags); in stm32_usart_unthrottle()
1026 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_unthrottle()
1027 if (stm32_port->cr3_irq) in stm32_usart_unthrottle()
1028 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
1030 stm32_port->throttled = false; in stm32_usart_unthrottle()
1036 if (stm32_port->rx_ch) in stm32_usart_unthrottle()
1039 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_unthrottle()
1046 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_rx()
1051 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_stop_rx()
1052 if (stm32_port->cr3_irq) in stm32_usart_stop_rx()
1053 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
1056 /* Handle breaks - ignored by us */
1064 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_startup()
1065 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_startup()
1066 const char *name = to_platform_device(port->dev)->name; in stm32_usart_startup()
1070 ret = request_irq(port->irq, stm32_usart_interrupt, in stm32_usart_startup()
1075 if (stm32_port->swap) { in stm32_usart_startup()
1076 val = readl_relaxed(port->membase + ofs->cr2); in stm32_usart_startup()
1078 writel_relaxed(val, port->membase + ofs->cr2); in stm32_usart_startup()
1080 stm32_port->throttled = false; in stm32_usart_startup()
1082 /* RX FIFO Flush */ in stm32_usart_startup()
1083 if (ofs->rqr != UNDEF_REG) in stm32_usart_startup()
1084 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); in stm32_usart_startup()
1086 if (stm32_port->rx_ch) { in stm32_usart_startup()
1089 free_irq(port->irq, port); in stm32_usart_startup()
1094 /* RX enabling */ in stm32_usart_startup()
1095 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); in stm32_usart_startup()
1096 stm32_usart_set_bits(port, ofs->cr1, val); in stm32_usart_startup()
1104 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_shutdown()
1105 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_shutdown()
1112 if (stm32_port->tx_ch) in stm32_usart_shutdown()
1113 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_shutdown()
1119 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_usart_shutdown()
1120 val |= BIT(cfg->uart_enable_bit); in stm32_usart_shutdown()
1121 if (stm32_port->fifoen) in stm32_usart_shutdown()
1124 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_usart_shutdown()
1130 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_shutdown()
1132 /* Disable RX DMA. */ in stm32_usart_shutdown()
1133 if (stm32_port->rx_ch) { in stm32_usart_shutdown()
1135 dmaengine_synchronize(stm32_port->rx_ch); in stm32_usart_shutdown()
1138 /* flush RX & TX FIFO */ in stm32_usart_shutdown()
1139 if (ofs->rqr != UNDEF_REG) in stm32_usart_shutdown()
1141 port->membase + ofs->rqr); in stm32_usart_shutdown()
1143 stm32_usart_clr_bits(port, ofs->cr1, val); in stm32_usart_shutdown()
1145 free_irq(port->irq, port); in stm32_usart_shutdown()
1153 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_termios()
1154 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_set_termios()
1155 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_set_termios()
1158 tcflag_t cflag = termios->c_cflag; in stm32_usart_set_termios()
1163 if (!stm32_port->hw_flow_control) in stm32_usart_set_termios()
1166 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_usart_set_termios()
1168 spin_lock_irqsave(&port->lock, flags); in stm32_usart_set_termios()
1170 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_set_termios()
1177 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_set_termios()
1180 writel_relaxed(0, port->membase + ofs->cr1); in stm32_usart_set_termios()
1182 /* flush RX & TX FIFO */ in stm32_usart_set_termios()
1183 if (ofs->rqr != UNDEF_REG) in stm32_usart_set_termios()
1185 port->membase + ofs->rqr); in stm32_usart_set_termios()
1188 if (stm32_port->fifoen) in stm32_usart_set_termios()
1190 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; in stm32_usart_set_termios()
1192 /* Tx and RX FIFO configuration */ in stm32_usart_set_termios()
1193 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
1195 if (stm32_port->fifoen) { in stm32_usart_set_termios()
1196 if (stm32_port->txftcfg >= 0) in stm32_usart_set_termios()
1197 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; in stm32_usart_set_termios()
1198 if (stm32_port->rxftcfg >= 0) in stm32_usart_set_termios()
1199 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; in stm32_usart_set_termios()
1206 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_usart_set_termios()
1222 } else if ((bits == 7) && cfg->has_7bits_data) { in stm32_usart_set_termios()
1225 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_usart_set_termios()
1229 termios->c_cflag = cflag; in stm32_usart_set_termios()
1237 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_usart_set_termios()
1238 (stm32_port->fifoen && in stm32_usart_set_termios()
1239 stm32_port->rxftcfg >= 0))) { in stm32_usart_set_termios()
1245 /* RX timeout irq to occur after last stop bit + bits */ in stm32_usart_set_termios()
1246 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_usart_set_termios()
1247 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_usart_set_termios()
1251 * wake up over usart, from low power until the DMA gets re-enabled by resume. in stm32_usart_set_termios()
1253 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_usart_set_termios()
1256 cr1 |= stm32_port->cr1_irq; in stm32_usart_set_termios()
1257 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
1262 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_usart_set_termios()
1264 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_usart_set_termios()
1268 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_usart_set_termios()
1279 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1283 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1288 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_usart_set_termios()
1292 port->read_status_mask = USART_SR_ORE; in stm32_usart_set_termios()
1293 if (termios->c_iflag & INPCK) in stm32_usart_set_termios()
1294 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1295 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_usart_set_termios()
1296 port->read_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1299 port->ignore_status_mask = 0; in stm32_usart_set_termios()
1300 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1301 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1302 if (termios->c_iflag & IGNBRK) { in stm32_usart_set_termios()
1303 port->ignore_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1308 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1309 port->ignore_status_mask |= USART_SR_ORE; in stm32_usart_set_termios()
1313 if ((termios->c_cflag & CREAD) == 0) in stm32_usart_set_termios()
1314 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_usart_set_termios()
1316 if (stm32_port->rx_ch) { in stm32_usart_set_termios()
1327 if (stm32_port->tx_ch) in stm32_usart_set_termios()
1330 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_set_termios()
1332 rs485conf->delay_rts_before_send, in stm32_usart_set_termios()
1333 rs485conf->delay_rts_after_send, in stm32_usart_set_termios()
1335 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_set_termios()
1337 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1340 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1349 if (stm32_port->wakeup_src) { in stm32_usart_set_termios()
1354 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
1355 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_usart_set_termios()
1356 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_set_termios()
1358 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_set_termios()
1359 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_set_termios()
1362 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_usart_set_termios()
1370 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_usart_type()
1385 port->type = PORT_STM32; in stm32_usart_config_port()
1392 return -EINVAL; in stm32_usart_verify_port()
1400 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_pm()
1401 const struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_usart_pm()
1406 pm_runtime_get_sync(port->dev); in stm32_usart_pm()
1409 spin_lock_irqsave(&port->lock, flags); in stm32_usart_pm()
1410 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_pm()
1411 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_pm()
1412 pm_runtime_put_sync(port->dev); in stm32_usart_pm()
1424 return clk_prepare_enable(stm32_port->clk); in stm32_usart_poll_init()
1430 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_poll_get_char()
1432 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) in stm32_usart_poll_get_char()
1435 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; in stm32_usart_poll_get_char()
1473 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
1485 /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */ in stm32_usart_get_ftcfg()
1486 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) in stm32_usart_get_ftcfg()
1493 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; in stm32_usart_get_ftcfg()
1495 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, in stm32_usart_get_ftcfg()
1500 *ftcfg = i - 1; in stm32_usart_get_ftcfg()
1502 *ftcfg = -EINVAL; in stm32_usart_get_ftcfg()
1507 clk_disable_unprepare(stm32port->clk); in stm32_usart_deinit_port()
1520 struct uart_port *port = &stm32port->port; in stm32_usart_init_port()
1528 port->iotype = UPIO_MEM; in stm32_usart_init_port()
1529 port->flags = UPF_BOOT_AUTOCONF; in stm32_usart_init_port()
1530 port->ops = &stm32_uart_ops; in stm32_usart_init_port()
1531 port->dev = &pdev->dev; in stm32_usart_init_port()
1532 port->fifosize = stm32port->info->cfg.fifosize; in stm32_usart_init_port()
1533 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_usart_init_port()
1534 port->irq = irq; in stm32_usart_init_port()
1535 port->rs485_config = stm32_usart_config_rs485; in stm32_usart_init_port()
1536 port->rs485_supported = stm32_rs485_supported; in stm32_usart_init_port()
1542 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && in stm32_usart_init_port()
1543 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); in stm32_usart_init_port()
1545 stm32port->swap = stm32port->info->cfg.has_swap && in stm32_usart_init_port()
1546 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); in stm32_usart_init_port()
1548 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_usart_init_port()
1549 if (stm32port->fifoen) { in stm32_usart_init_port()
1550 stm32_usart_get_ftcfg(pdev, "rx-threshold", in stm32_usart_init_port()
1551 &stm32port->rxftcfg); in stm32_usart_init_port()
1552 stm32_usart_get_ftcfg(pdev, "tx-threshold", in stm32_usart_init_port()
1553 &stm32port->txftcfg); in stm32_usart_init_port()
1556 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_usart_init_port()
1557 if (IS_ERR(port->membase)) in stm32_usart_init_port()
1558 return PTR_ERR(port->membase); in stm32_usart_init_port()
1559 port->mapbase = res->start; in stm32_usart_init_port()
1561 spin_lock_init(&port->lock); in stm32_usart_init_port()
1563 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_usart_init_port()
1564 if (IS_ERR(stm32port->clk)) in stm32_usart_init_port()
1565 return PTR_ERR(stm32port->clk); in stm32_usart_init_port()
1568 ret = clk_prepare_enable(stm32port->clk); in stm32_usart_init_port()
1572 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_usart_init_port()
1573 if (!stm32port->port.uartclk) { in stm32_usart_init_port()
1574 ret = -EINVAL; in stm32_usart_init_port()
1578 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_usart_init_port()
1579 if (IS_ERR(stm32port->gpios)) { in stm32_usart_init_port()
1580 ret = PTR_ERR(stm32port->gpios); in stm32_usart_init_port()
1585 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" in stm32_usart_init_port()
1588 if (stm32port->hw_flow_control) { in stm32_usart_init_port()
1589 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_usart_init_port()
1590 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_usart_init_port()
1591 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_usart_init_port()
1592 ret = -EINVAL; in stm32_usart_init_port()
1600 clk_disable_unprepare(stm32port->clk); in stm32_usart_init_port()
1607 struct device_node *np = pdev->dev.of_node; in stm32_usart_of_get_port()
1615 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_usart_of_get_port()
1623 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_usart_of_get_port()
1624 of_property_read_bool (np, "uart-has-rtscts"); in stm32_usart_of_get_port()
1634 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1635 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1636 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1646 if (stm32port->rx_buf) in stm32_usart_of_dma_rx_remove()
1647 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, in stm32_usart_of_dma_rx_remove()
1648 stm32port->rx_dma_buf); in stm32_usart_of_dma_rx_remove()
1654 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_rx_probe()
1655 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_rx_probe()
1656 struct device *dev = &pdev->dev; in stm32_usart_of_dma_rx_probe()
1660 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, in stm32_usart_of_dma_rx_probe()
1661 &stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1663 if (!stm32port->rx_buf) in stm32_usart_of_dma_rx_probe()
1664 return -ENOMEM; in stm32_usart_of_dma_rx_probe()
1668 config.src_addr = port->mapbase + ofs->rdr; in stm32_usart_of_dma_rx_probe()
1671 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_usart_of_dma_rx_probe()
1673 dev_err(dev, "rx dma channel config failed\n"); in stm32_usart_of_dma_rx_probe()
1684 if (stm32port->tx_buf) in stm32_usart_of_dma_tx_remove()
1685 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, in stm32_usart_of_dma_tx_remove()
1686 stm32port->tx_dma_buf); in stm32_usart_of_dma_tx_remove()
1692 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_tx_probe()
1693 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_tx_probe()
1694 struct device *dev = &pdev->dev; in stm32_usart_of_dma_tx_probe()
1698 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, in stm32_usart_of_dma_tx_probe()
1699 &stm32port->tx_dma_buf, in stm32_usart_of_dma_tx_probe()
1701 if (!stm32port->tx_buf) in stm32_usart_of_dma_tx_probe()
1702 return -ENOMEM; in stm32_usart_of_dma_tx_probe()
1706 config.dst_addr = port->mapbase + ofs->tdr; in stm32_usart_of_dma_tx_probe()
1709 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_usart_of_dma_tx_probe()
1711 dev_err(dev, "tx dma channel config failed\n"); in stm32_usart_of_dma_tx_probe()
1726 return -ENODEV; in stm32_usart_serial_probe()
1728 stm32port->info = of_device_get_match_data(&pdev->dev); in stm32_usart_serial_probe()
1729 if (!stm32port->info) in stm32_usart_serial_probe()
1730 return -EINVAL; in stm32_usart_serial_probe()
1732 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); in stm32_usart_serial_probe()
1733 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) in stm32_usart_serial_probe()
1734 return -EPROBE_DEFER; in stm32_usart_serial_probe()
1736 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1737 if (IS_ERR(stm32port->rx_ch)) in stm32_usart_serial_probe()
1738 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1740 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); in stm32_usart_serial_probe()
1741 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { in stm32_usart_serial_probe()
1742 ret = -EPROBE_DEFER; in stm32_usart_serial_probe()
1745 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1746 if (IS_ERR(stm32port->tx_ch)) in stm32_usart_serial_probe()
1747 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1753 if (stm32port->wakeup_src) { in stm32_usart_serial_probe()
1754 device_set_wakeup_capable(&pdev->dev, true); in stm32_usart_serial_probe()
1755 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); in stm32_usart_serial_probe()
1760 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1762 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1763 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1766 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1768 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1769 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1772 if (!stm32port->rx_ch) in stm32_usart_serial_probe()
1773 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); in stm32_usart_serial_probe()
1774 if (!stm32port->tx_ch) in stm32_usart_serial_probe()
1775 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); in stm32_usart_serial_probe()
1777 platform_set_drvdata(pdev, &stm32port->port); in stm32_usart_serial_probe()
1779 pm_runtime_get_noresume(&pdev->dev); in stm32_usart_serial_probe()
1780 pm_runtime_set_active(&pdev->dev); in stm32_usart_serial_probe()
1781 pm_runtime_enable(&pdev->dev); in stm32_usart_serial_probe()
1783 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_usart_serial_probe()
1787 pm_runtime_put_sync(&pdev->dev); in stm32_usart_serial_probe()
1792 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_probe()
1793 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_probe()
1794 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_probe()
1796 if (stm32port->tx_ch) in stm32_usart_serial_probe()
1798 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1801 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1802 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_probe()
1805 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1806 device_set_wakeup_capable(&pdev->dev, false); in stm32_usart_serial_probe()
1811 if (stm32port->tx_ch) in stm32_usart_serial_probe()
1812 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1815 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1816 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1825 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_remove()
1828 pm_runtime_get_sync(&pdev->dev); in stm32_usart_serial_remove()
1831 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_remove()
1832 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_remove()
1833 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_remove()
1835 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); in stm32_usart_serial_remove()
1837 if (stm32_port->tx_ch) { in stm32_usart_serial_remove()
1839 dma_release_channel(stm32_port->tx_ch); in stm32_usart_serial_remove()
1842 if (stm32_port->rx_ch) { in stm32_usart_serial_remove()
1844 dma_release_channel(stm32_port->rx_ch); in stm32_usart_serial_remove()
1847 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_serial_remove()
1852 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_serial_remove()
1854 if (stm32_port->wakeup_src) { in stm32_usart_serial_remove()
1855 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_remove()
1856 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_remove()
1867 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_putchar()
1871 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, in stm32_usart_console_putchar()
1875 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); in stm32_usart_console_putchar()
1878 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_console_putchar()
1885 struct uart_port *port = &stm32_ports[co->index].port; in stm32_usart_console_write()
1887 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_write()
1888 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_console_write()
1894 locked = spin_trylock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1896 spin_lock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1899 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_console_write()
1901 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_usart_console_write()
1902 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1907 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1910 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_console_write()
1921 if (co->index >= STM32_MAX_PORTS) in stm32_usart_console_setup()
1922 return -ENODEV; in stm32_usart_console_setup()
1924 stm32port = &stm32_ports[co->index]; in stm32_usart_console_setup()
1929 * this to be called during the uart port registration when the in stm32_usart_console_setup()
1932 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) in stm32_usart_console_setup()
1933 return -ENXIO; in stm32_usart_console_setup()
1938 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_usart_console_setup()
1947 .index = -1,
1960 struct stm32_usart_info *info = port->private_data; in early_stm32_usart_console_putchar()
1962 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) in early_stm32_usart_console_putchar()
1965 writel_relaxed(ch, port->membase + info->ofs.tdr); in early_stm32_usart_console_putchar()
1970 struct earlycon_device *device = console->data; in early_stm32_serial_write()
1971 struct uart_port *port = &device->port; in early_stm32_serial_write()
1978 if (!(device->port.membase || device->port.iobase)) in early_stm32_h7_serial_setup()
1979 return -ENODEV; in early_stm32_h7_serial_setup()
1980 device->port.private_data = &stm32h7_info; in early_stm32_h7_serial_setup()
1981 device->con->write = early_stm32_serial_write; in early_stm32_h7_serial_setup()
1987 if (!(device->port.membase || device->port.iobase)) in early_stm32_f7_serial_setup()
1988 return -ENODEV; in early_stm32_f7_serial_setup()
1989 device->port.private_data = &stm32f7_info; in early_stm32_f7_serial_setup()
1990 device->con->write = early_stm32_serial_write; in early_stm32_f7_serial_setup()
1996 if (!(device->port.membase || device->port.iobase)) in early_stm32_f4_serial_setup()
1997 return -ENODEV; in early_stm32_f4_serial_setup()
1998 device->port.private_data = &stm32f4_info; in early_stm32_f4_serial_setup()
1999 device->con->write = early_stm32_serial_write; in early_stm32_f4_serial_setup()
2003 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
2004 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
2005 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
2021 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_en_wakeup()
2022 struct tty_port *tport = &port->state->port; in stm32_usart_serial_en_wakeup()
2027 if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) in stm32_usart_serial_en_wakeup()
2031 * Enable low-power wake-up and wake-up irq if argument is set to in stm32_usart_serial_en_wakeup()
2032 * "enable", disable low-power wake-up and wake-up irq otherwise in stm32_usart_serial_en_wakeup()
2035 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2036 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2037 mctrl_gpio_enable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2041 * entering low-power mode and re-enabled when exiting from in stm32_usart_serial_en_wakeup()
2042 * low-power mode. in stm32_usart_serial_en_wakeup()
2044 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2045 spin_lock_irqsave(&port->lock, flags); in stm32_usart_serial_en_wakeup()
2046 /* Poll data from DMA RX buffer if any */ in stm32_usart_serial_en_wakeup()
2055 /* Poll data from RX FIFO if any */ in stm32_usart_serial_en_wakeup()
2058 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2063 mctrl_gpio_disable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2064 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2065 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2122 clk_disable_unprepare(stm32port->clk); in stm32_usart_runtime_suspend()
2133 return clk_prepare_enable(stm32port->clk); in stm32_usart_runtime_resume()