tty/serial/sifive.c

3  * SiFive UART driver
5  * Copyright (C) 2018-2019 SiFive
12  * - drivers/pwm/pwm-sifive.c
16  *   SiFive FE310-G000 v2p3
18  *   https://github.com/sifive/sifive-blocks/
20  * The SiFive UART design is not 8250-compatible.  The following common
117 #define SIFIVE_SERIAL_NAME			"sifive-serial"
119 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
145  * Configuration data specific to this SiFive UART.
178  * __ssp_early_writel() - write to a SiFive serial port register (early)
195  * __ssp_early_readl() - read from a SiFive serial port register (early)
215  * __ssp_writel() - write to a SiFive serial port register
231  * __ssp_readl() - read from a SiFive serial port register
285  * transmit buffer to the SiFive UART TX FIFO.
304  * on the SiFive UART referred to by @ssp.
320  * on the SiFive UART referred to by @ssp.
368  * Try to read a byte from the SiFive UART RX FIFO, referenced by
398  * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
444  * SiFive UART described by @ssp and program it into the UART.  There may
463  * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
700 	return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;  in sifive_serial_type()
762 OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
763 OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
1040 	{ .compatible = "sifive,fu540-c000-uart0" },
1041 	{ .compatible = "sifive,uart0" },
1085 MODULE_DESCRIPTION("SiFive UART serial driver");