Lines Matching full:sampling

27 	HSSRR,				/* Sampling Rate Register */
52 #define SCSMR_SRC_MASK	0x0700	/* Sampling Control */
53 #define SCSMR_SRC_16	0x0000	/* Sampling rate 1/16 */
54 #define SCSMR_SRC_5	0x0100	/* Sampling rate 1/5 */
55 #define SCSMR_SRC_7	0x0200	/* Sampling rate 1/7 */
56 #define SCSMR_SRC_11	0x0300	/* Sampling rate 1/11 */
57 #define SCSMR_SRC_13	0x0400	/* Sampling rate 1/13 */
58 #define SCSMR_SRC_17	0x0500	/* Sampling rate 1/17 */
59 #define SCSMR_SRC_19	0x0600	/* Sampling rate 1/19 */
60 #define SCSMR_SRC_27	0x0700	/* Sampling rate 1/27 */
135 #define HSCIF_SRE	BIT(15)	/* Sampling Rate Register Enable */
136 #define HSCIF_SRDE	BIT(14) /* Sampling Point Register Enable */
158  * the sampling clock. It outputs either its frequency divided clock, or the