Lines Matching refs:RP2_TXRX_CTL
113 #define RP2_TXRX_CTL 0x014 macro
300 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, in rp2_uart_set_mctrl()
309 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m); in rp2_uart_start_tx()
314 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m); in rp2_uart_stop_tx()
319 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m); in rp2_uart_stop_rx()
327 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m, in rp2_uart_break_ctl()
334 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m); in rp2_uart_enable_ms()
355 rp2_rmw(up, RP2_TXRX_CTL, in __rp2_uart_set_termios()
503 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m); in rp2_uart_startup()
504 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m, in rp2_uart_startup()
615 writel(0, up->base + RP2_TXRX_CTL); in rp2_init_port()
631 rp2_rmw_set(up, RP2_TXRX_CTL, in rp2_init_port()