Lines Matching +full:port +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
12 * rocketport_infinity_express-linux-1.20.tar.gz
13 * Copyright (C) 2004-2011 Comtrol, Inc.
44 #define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
75 /* port registers */
84 /* This lets uart_insert_char() drop bytes received on a !CREAD port */
179 struct uart_port port; member
184 void __iomem *base; member
206 *ports = id->driver_data >> 8; in rp2_decode_cap()
207 *smpte = id->driver_data & 0xff; in rp2_decode_cap()
215 int ret = -ENOSPC; in rp2_alloc_ports()
228 static inline struct rp2_uart_port *port_to_up(struct uart_port *port) in port_to_up() argument
230 return container_of(port, struct rp2_uart_port, port); in port_to_up()
236 u32 tmp = readl(up->base + reg); in rp2_rmw()
239 writel(tmp, up->base + reg); in rp2_rmw()
257 spin_lock_irqsave(&up->card->card_lock, flags); in rp2_mask_ch_irq()
259 irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK); in rp2_mask_ch_irq()
264 writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK); in rp2_mask_ch_irq()
266 spin_unlock_irqrestore(&up->card->card_lock, flags); in rp2_mask_ch_irq()
269 static unsigned int rp2_uart_tx_empty(struct uart_port *port) in rp2_uart_tx_empty() argument
271 struct rp2_uart_port *up = port_to_up(port); in rp2_uart_tx_empty()
279 spin_lock_irqsave(&up->port.lock, flags); in rp2_uart_tx_empty()
280 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT); in rp2_uart_tx_empty()
281 spin_unlock_irqrestore(&up->port.lock, flags); in rp2_uart_tx_empty()
286 static unsigned int rp2_uart_get_mctrl(struct uart_port *port) in rp2_uart_get_mctrl() argument
288 struct rp2_uart_port *up = port_to_up(port); in rp2_uart_get_mctrl()
291 status = readl(up->base + RP2_CHAN_STAT); in rp2_uart_get_mctrl()
298 static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) in rp2_uart_set_mctrl() argument
300 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, in rp2_uart_set_mctrl()
307 static void rp2_uart_start_tx(struct uart_port *port) in rp2_uart_start_tx() argument
309 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m); in rp2_uart_start_tx()
312 static void rp2_uart_stop_tx(struct uart_port *port) in rp2_uart_stop_tx() argument
314 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m); in rp2_uart_stop_tx()
317 static void rp2_uart_stop_rx(struct uart_port *port) in rp2_uart_stop_rx() argument
319 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m); in rp2_uart_stop_rx()
322 static void rp2_uart_break_ctl(struct uart_port *port, int break_state) in rp2_uart_break_ctl() argument
326 spin_lock_irqsave(&port->lock, flags); in rp2_uart_break_ctl()
327 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m, in rp2_uart_break_ctl()
329 spin_unlock_irqrestore(&port->lock, flags); in rp2_uart_break_ctl()
332 static void rp2_uart_enable_ms(struct uart_port *port) in rp2_uart_enable_ms() argument
334 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m); in rp2_uart_enable_ms()
342 /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */ in __rp2_uart_set_termios()
343 writew(baud_div - 1, up->base + RP2_BAUD); in __rp2_uart_set_termios()
368 up->ucode + RP2_TX_SWFLOW); in __rp2_uart_set_termios()
370 up->ucode + RP2_RX_SWFLOW); in __rp2_uart_set_termios()
373 static void rp2_uart_set_termios(struct uart_port *port, struct ktermios *new, in rp2_uart_set_termios() argument
376 struct rp2_uart_port *up = port_to_up(port); in rp2_uart_set_termios()
380 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); in rp2_uart_set_termios()
381 baud_div = uart_get_divisor(port, baud); in rp2_uart_set_termios()
386 spin_lock_irqsave(&port->lock, flags); in rp2_uart_set_termios()
389 port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ; in rp2_uart_set_termios()
391 __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div); in rp2_uart_set_termios()
392 uart_update_timeout(port, new->c_cflag, baud); in rp2_uart_set_termios()
394 spin_unlock_irqrestore(&port->lock, flags); in rp2_uart_set_termios()
399 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT); in rp2_rx_chars()
400 struct tty_port *port = &up->port.state->port; in rp2_rx_chars() local
402 for (; bytes != 0; bytes--) { in rp2_rx_chars()
403 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ; in rp2_rx_chars()
407 if (!uart_handle_sysrq_char(&up->port, ch)) in rp2_rx_chars()
408 uart_insert_char(&up->port, byte, 0, ch, in rp2_rx_chars()
419 uart_insert_char(&up->port, byte, in rp2_rx_chars()
422 up->port.icount.rx++; in rp2_rx_chars()
425 tty_flip_buffer_push(port); in rp2_rx_chars()
432 uart_port_tx_limited(&up->port, ch, in rp2_tx_chars()
433 FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT), in rp2_tx_chars()
435 writeb(ch, up->base + RP2_DATA_BYTE), in rp2_tx_chars()
443 spin_lock(&up->port.lock); in rp2_ch_interrupt()
446 * The IRQ status bits are clear-on-write. Other status bits in in rp2_ch_interrupt()
449 status = readl(up->base + RP2_CHAN_STAT); in rp2_ch_interrupt()
450 writel(status, up->base + RP2_CHAN_STAT); in rp2_ch_interrupt()
457 wake_up_interruptible(&up->port.state->port.delta_msr_wait); in rp2_ch_interrupt()
459 spin_unlock(&up->port.lock); in rp2_ch_interrupt()
464 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); in rp2_asic_interrupt() local
466 unsigned long status = readl(base + RP2_CH_IRQ_STAT) & in rp2_asic_interrupt()
467 ~readl(base + RP2_CH_IRQ_MASK); in rp2_asic_interrupt()
470 rp2_ch_interrupt(&card->ports[ch]); in rp2_asic_interrupt()
482 if (card->n_ports >= PORTS_PER_ASIC) in rp2_uart_interrupt()
492 readl(up->base + RP2_UART_CTL); in rp2_flush_fifos()
498 static int rp2_uart_startup(struct uart_port *port) in rp2_uart_startup() argument
500 struct rp2_uart_port *up = port_to_up(port); in rp2_uart_startup()
507 rp2_mask_ch_irq(up, up->idx, 1); in rp2_uart_startup()
512 static void rp2_uart_shutdown(struct uart_port *port) in rp2_uart_shutdown() argument
514 struct rp2_uart_port *up = port_to_up(port); in rp2_uart_shutdown()
517 rp2_uart_break_ctl(port, 0); in rp2_uart_shutdown()
519 spin_lock_irqsave(&port->lock, flags); in rp2_uart_shutdown()
520 rp2_mask_ch_irq(up, up->idx, 0); in rp2_uart_shutdown()
522 spin_unlock_irqrestore(&port->lock, flags); in rp2_uart_shutdown()
525 static const char *rp2_uart_type(struct uart_port *port) in rp2_uart_type() argument
527 return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL; in rp2_uart_type()
530 static void rp2_uart_release_port(struct uart_port *port) in rp2_uart_release_port() argument
535 static int rp2_uart_request_port(struct uart_port *port) in rp2_uart_request_port() argument
541 static void rp2_uart_config_port(struct uart_port *port, int flags) in rp2_uart_config_port() argument
544 port->type = PORT_RP2; in rp2_uart_config_port()
547 static int rp2_uart_verify_port(struct uart_port *port, in rp2_uart_verify_port() argument
550 if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2) in rp2_uart_verify_port()
551 return -EINVAL; in rp2_uart_verify_port()
577 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id); in rp2_reset_asic() local
580 writew(1, base + RP2_GLOBAL_CMD); in rp2_reset_asic()
582 readw(base + RP2_GLOBAL_CMD); in rp2_reset_asic()
583 writel(0, base + RP2_CLK_PRESCALER); in rp2_reset_asic()
586 clk_cfg = readw(base + RP2_ASIC_CFG); in rp2_reset_asic()
588 writew(clk_cfg, base + RP2_ASIC_CFG); in rp2_reset_asic()
591 writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK); in rp2_reset_asic()
592 writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ); in rp2_reset_asic()
597 writel(4, card->bar0 + RP2_FPGA_CTL0); in rp2_init_card()
598 writel(0, card->bar0 + RP2_FPGA_CTL1); in rp2_init_card()
601 if (card->n_ports >= PORTS_PER_ASIC) in rp2_init_card()
604 writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK); in rp2_init_card()
611 writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL); in rp2_init_port()
612 readl(up->base + RP2_UART_CTL); in rp2_init_port()
615 writel(0, up->base + RP2_TXRX_CTL); in rp2_init_port()
616 writel(0, up->base + RP2_UART_CTL); in rp2_init_port()
617 readl(up->base + RP2_UART_CTL); in rp2_init_port()
622 for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++) in rp2_init_port()
623 writeb(fw->data[i], up->ucode + i); in rp2_init_port()
626 rp2_uart_set_mctrl(&up->port, 0); in rp2_init_port()
628 writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO); in rp2_init_port()
639 for (i = 0; i < card->initialized_ports; i++) in rp2_remove_ports()
640 uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port); in rp2_remove_ports()
641 card->initialized_ports = 0; in rp2_remove_ports()
649 phys_base = pci_resource_start(card->pdev, 1); in rp2_load_firmware()
651 for (i = 0; i < card->n_ports; i++) { in rp2_load_firmware()
652 struct rp2_uart_port *rp = &card->ports[i]; in rp2_load_firmware()
656 rp->asic_base = card->bar1; in rp2_load_firmware()
657 rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING; in rp2_load_firmware()
658 rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING; in rp2_load_firmware()
659 rp->card = card; in rp2_load_firmware()
660 rp->idx = j; in rp2_load_firmware()
662 p = &rp->port; in rp2_load_firmware()
663 p->line = card->minor_start + i; in rp2_load_firmware()
664 p->dev = &card->pdev->dev; in rp2_load_firmware()
665 p->type = PORT_RP2; in rp2_load_firmware()
666 p->iotype = UPIO_MEM32; in rp2_load_firmware()
667 p->uartclk = UART_CLOCK; in rp2_load_firmware()
668 p->regshift = 2; in rp2_load_firmware()
669 p->fifosize = FIFO_SIZE; in rp2_load_firmware()
670 p->ops = &rp2_uart_ops; in rp2_load_firmware()
671 p->irq = card->pdev->irq; in rp2_load_firmware()
672 p->membase = rp->base; in rp2_load_firmware()
673 p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING; in rp2_load_firmware()
676 rp->asic_base += RP2_ASIC_SPACING; in rp2_load_firmware()
677 rp->base += RP2_ASIC_SPACING; in rp2_load_firmware()
678 rp->ucode += RP2_ASIC_SPACING; in rp2_load_firmware()
679 p->mapbase += RP2_ASIC_SPACING; in rp2_load_firmware()
685 dev_err(&card->pdev->dev, in rp2_load_firmware()
686 "error registering port %d: %d\n", i, rc); in rp2_load_firmware()
690 card->initialized_ports++; in rp2_load_firmware()
705 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL); in rp2_probe()
707 return -ENOMEM; in rp2_probe()
709 spin_lock_init(&card->card_lock); in rp2_probe()
720 card->bar0 = bars[0]; in rp2_probe()
721 card->bar1 = bars[1]; in rp2_probe()
722 card->pdev = pdev; in rp2_probe()
724 rp2_decode_cap(id, &card->n_ports, &card->smpte); in rp2_probe()
725 dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports); in rp2_probe()
727 card->minor_start = rp2_alloc_ports(card->n_ports); in rp2_probe()
728 if (card->minor_start < 0) { in rp2_probe()
729 dev_err(&pdev->dev, in rp2_probe()
731 return -EINVAL; in rp2_probe()
736 ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports), in rp2_probe()
739 return -ENOMEM; in rp2_probe()
740 card->ports = ports; in rp2_probe()
742 rc = request_firmware(&fw, RP2_FW_NAME, &pdev->dev); in rp2_probe()
744 dev_err(&pdev->dev, "cannot find '%s' firmware image\n", in rp2_probe()
755 rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt, in rp2_probe()