18 #include <linux/soc/qcom/geni-se.h>
119 	struct geni_se se;  member
198 	port->se.base = uport->membase;  in qcom_geni_serial_request_port()
403 		geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);  in qcom_geni_serial_poll_init()
503 		geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_console_write()
506 			geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_console_write()
609 		geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr,  in qcom_geni_serial_stop_tx_dma()
615 	geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_dma()
620 		geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_dma()
648 	ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail],  in qcom_geni_serial_start_tx_dma()
651 		dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret);  in qcom_geni_serial_start_tx_dma()
687 	geni_se_cancel_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_fifo()
690 		geni_se_abort_m_cmd(&port->se);  in qcom_geni_serial_stop_tx_fifo()
739 	geni_se_cancel_s_cmd(&port->se);  in qcom_geni_serial_stop_rx_fifo()
764 	geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);  in qcom_geni_serial_start_rx_fifo()
783 	geni_se_cancel_s_cmd(&port->se);  in qcom_geni_serial_stop_rx_dma()
800 		geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr,  in qcom_geni_serial_stop_rx_dma()
814 	geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN);  in qcom_geni_serial_start_rx_dma()
816 	ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,  in qcom_geni_serial_start_rx_dma()
820 		dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);  in qcom_geni_serial_start_rx_dma()
837 	geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE);  in qcom_geni_serial_handle_rx_dma()
849 	ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,  in qcom_geni_serial_handle_rx_dma()
853 		dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);  in qcom_geni_serial_handle_rx_dma()
967 	geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining);  in qcom_geni_serial_handle_tx_dma()
1068 	port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);  in setup_fifos()
1069 	port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);  in setup_fifos()
1070 	port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);  in setup_fifos()
1110 	proto = geni_se_read_proto(&port->se);  in qcom_geni_serial_port_setup()
1143 	geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_port_setup()
1145 	geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);  in qcom_geni_serial_port_setup()
1146 	geni_se_select_mode(&port->se, port->dev_data->mode);  in qcom_geni_serial_port_setup()
1257 	ver = geni_se_get_qup_hw_version(&port->se);  in qcom_geni_serial_set_termios()
1261 	clk_rate = get_clk_div_rate(port->se.clk, baud,  in qcom_geni_serial_set_termios()
1264 		dev_err(port->se.dev,  in qcom_geni_serial_set_termios()
1270 	dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",  in qcom_geni_serial_set_termios()
1285 	port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;  in qcom_geni_serial_set_termios()
1286 	port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);  in qcom_geni_serial_set_termios()
1287 	geni_icc_set_bw(&port->se);  in qcom_geni_serial_set_termios()
1424 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1427 	geni_se_setup_s_cmd(se, UART_START_READ, 0);  in qcom_geni_serial_enable_early_read()
1431 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,  in qcom_geni_serial_enable_early_read()  argument
1447 	struct geni_se se;  in qcom_geni_serial_earlycon_setup()  local
1454 	memset(&se, 0, sizeof(se));  in qcom_geni_serial_earlycon_setup()
1455 	se.base = uport->membase;  in qcom_geni_serial_earlycon_setup()
1456 	if (geni_se_read_proto(&se) != GENI_SE_UART)  in qcom_geni_serial_earlycon_setup()
1471 	geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,  in qcom_geni_serial_earlycon_setup()
1473 	geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);  in qcom_geni_serial_earlycon_setup()
1474 	geni_se_select_mode(&se, GENI_SE_FIFO);  in qcom_geni_serial_earlycon_setup()
1486 	qcom_geni_serial_enable_early_read(&se, dev->con);  in qcom_geni_serial_earlycon_setup()
1548 		geni_icc_enable(&port->se);  in qcom_geni_serial_pm()
1551 		geni_se_resources_on(&port->se);  in qcom_geni_serial_pm()
1554 		geni_se_resources_off(&port->se);  in qcom_geni_serial_pm()
1556 		geni_icc_disable(&port->se);  in qcom_geni_serial_pm()
1637 	port->se.dev = &pdev->dev;  in qcom_geni_serial_probe()
1638 	port->se.wrapper = dev_get_drvdata(pdev->dev.parent);  in qcom_geni_serial_probe()
1639 	port->se.clk = devm_clk_get(&pdev->dev, "se");  in qcom_geni_serial_probe()
1640 	if (IS_ERR(port->se.clk)) {  in qcom_geni_serial_probe()
1641 		ret = PTR_ERR(port->se.clk);  in qcom_geni_serial_probe()
1642 		dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);  in qcom_geni_serial_probe()
1662 	ret = geni_icc_get(&port->se, NULL);  in qcom_geni_serial_probe()
1665 	port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1666 	port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in qcom_geni_serial_probe()
1669 	ret = geni_icc_set_bw(&port->se);  in qcom_geni_serial_probe()
1694 	ret = devm_pm_opp_set_clkname(&pdev->dev, "se");  in qcom_geni_serial_probe()
1757 		geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);  in qcom_geni_serial_sys_suspend()
1758 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_suspend()
1772 		geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);  in qcom_geni_serial_sys_resume()
1773 		geni_icc_set_bw(&port->se);  in qcom_geni_serial_sys_resume()