1065 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_prepare()  local
1091 	if (uart_clock_base->configured) {  in mvebu_uart_clock_prepare()
1096 	parent_clock_idx = uart_clock_base->parent_idx;  in mvebu_uart_clock_prepare()
1097 	parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx];  in mvebu_uart_clock_prepare()
1099 	val = readl(uart_clock_base->reg1);  in mvebu_uart_clock_prepare()
1101 	if (uart_clock_base->div > CLK_TBG_DIV1_MAX) {  in mvebu_uart_clock_prepare()
1103 		d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX;  in mvebu_uart_clock_prepare()
1105 		d1 = uart_clock_base->div;  in mvebu_uart_clock_prepare()
1119 	prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx];  in mvebu_uart_clock_prepare()
1147 	writel(val, uart_clock_base->reg1);  in mvebu_uart_clock_prepare()
1151 		val = readl(uart_clock_base->reg2);  in mvebu_uart_clock_prepare()
1160 		writel(val, uart_clock_base->reg2);  in mvebu_uart_clock_prepare()
1163 	uart_clock_base->configured = true;  in mvebu_uart_clock_prepare()
1173 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_enable()  local
1180 	val = readl(uart_clock_base->reg1);  in mvebu_uart_clock_enable()
1187 	writel(val, uart_clock_base->reg1);  in mvebu_uart_clock_enable()
1197 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_disable()  local
1204 	val = readl(uart_clock_base->reg1);  in mvebu_uart_clock_disable()
1211 	writel(val, uart_clock_base->reg1);  in mvebu_uart_clock_disable()
1219 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_is_enabled()  local
1223 	val = readl(uart_clock_base->reg1);  in mvebu_uart_clock_is_enabled()
1234 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_save_context()  local
1239 	uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1);  in mvebu_uart_clock_save_context()
1240 	uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2);  in mvebu_uart_clock_save_context()
1249 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_restore_context()  local
1254 	writel(uart_clock->pm_context_reg1, uart_clock_base->reg1);  in mvebu_uart_clock_restore_context()
1255 	writel(uart_clock->pm_context_reg2, uart_clock_base->reg2);  in mvebu_uart_clock_restore_context()
1263 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_recalc_rate()  local
1266 	return parent_rate / uart_clock_base->div;  in mvebu_uart_clock_recalc_rate()
1273 	struct mvebu_uart_clock_base *uart_clock_base =  in mvebu_uart_clock_round_rate()  local
1276 	return *parent_rate / uart_clock_base->div;  in mvebu_uart_clock_round_rate()
1328 	struct mvebu_uart_clock_base *uart_clock_base;  in mvebu_uart_clock_probe()  local
1337 		     ARRAY_SIZE(uart_clock_base->clocks));  in mvebu_uart_clock_probe()
1339 		     ARRAY_SIZE(uart_clock_base->parent_rates));  in mvebu_uart_clock_probe()
1341 	uart_clock_base = devm_kzalloc(dev,  in mvebu_uart_clock_probe()
1342 				       sizeof(*uart_clock_base),  in mvebu_uart_clock_probe()
1344 	if (!uart_clock_base)  in mvebu_uart_clock_probe()
1361 	uart_clock_base->reg1 = devm_ioremap(dev, res->start,  in mvebu_uart_clock_probe()
1363 	if (!uart_clock_base->reg1)  in mvebu_uart_clock_probe()
1380 	uart_clock_base->reg2 = devm_ioremap(dev, res->start,  in mvebu_uart_clock_probe()
1382 	if (!uart_clock_base->reg2)  in mvebu_uart_clock_probe()
1394 		hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw;  in mvebu_uart_clock_probe()
1395 		uart_clock_base->clocks[i].clock_idx = i;  in mvebu_uart_clock_probe()
1417 		uart_clock_base->parent_rates[i] = rate;  in mvebu_uart_clock_probe()
1473 	uart_clock_base->parent_idx = parent_clk_idx;  in mvebu_uart_clock_probe()
1474 	uart_clock_base->div = div;  in mvebu_uart_clock_probe()
1481 				&uart_clock_base->clocks[i],  in mvebu_uart_clock_probe()