Lines Matching +full:tx +full:- +full:clk +full:- +full:100 +full:- +full:inverted
1 // SPDX-License-Identifier: GPL-2.0+
21 #include <linux/clk.h>
30 #include <linux/dma-mapping.h>
33 #include <linux/dma/imx-dma.h>
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
154 #define UTS_LOOP (1<<12) /* Loop tx and rx */
161 /* We've been assigned a range on the "Low-density serial ports" major */
170 * filling the TX fifo incase CTS has been dropped.
174 #define DRIVER_NAME "IMX-uart"
208 struct clk *clk_ipg;
209 struct clk *clk_per;
265 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
266 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
267 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
268 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
275 writel(val, sport->port.membase + offset); in imx_uart_writel()
280 return readl(sport->port.membase + offset); in imx_uart_readl()
285 return sport->devdata->uts_reg; in imx_uart_uts_reg()
290 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
301 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
302 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
303 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
310 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
311 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
312 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
321 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
330 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
349 * and UTS[6-3]". in imx_uart_soft_reset()
362 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_soft_reset()
370 sport->idle_counter = 0; in imx_uart_soft_reset()
394 if (sport->dma_is_enabled) { in imx_uart_start_rx()
413 if (sport->tx_state == OFF) in imx_uart_stop_tx()
417 * We are maybe in the SMP context, so if the DMA TX thread is running in imx_uart_stop_tx()
420 if (sport->dma_is_txing) in imx_uart_stop_tx()
437 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
438 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
439 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
441 if (port->rs485.delay_rts_after_send > 0) { in imx_uart_stop_tx()
442 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
443 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
450 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
451 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
454 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
457 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
463 if (!port->rs485_rx_during_tx_gpio) in imx_uart_stop_tx()
466 sport->tx_state = OFF; in imx_uart_stop_tx()
469 sport->tx_state = OFF; in imx_uart_stop_tx()
482 if (sport->dma_is_enabled) { in imx_uart_stop_rx_with_loopback_ctrl()
493 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_stop_rx_with_loopback_ctrl()
494 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_stop_rx_with_loopback_ctrl()
495 sport->have_rtscts && !sport->have_rtsgpio && loopback) { in imx_uart_stop_rx_with_loopback_ctrl()
522 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
524 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
532 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
534 if (sport->port.x_char) { in imx_uart_transmit_buffer()
536 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
537 sport->port.icount.tx++; in imx_uart_transmit_buffer()
538 sport->port.x_char = 0; in imx_uart_transmit_buffer()
542 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
543 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
547 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
550 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
551 * and the TX IRQ is disabled. in imx_uart_transmit_buffer()
555 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
568 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
570 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
571 uart_xmit_advance(&sport->port, 1); in imx_uart_transmit_buffer()
575 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
578 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
584 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
585 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
589 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
591 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
597 uart_xmit_advance(&sport->port, sport->tx_bytes); in imx_uart_dma_tx_callback()
599 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
601 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
604 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
606 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
608 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
614 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
620 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
621 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
623 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
624 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
628 if (sport->dma_is_txing) in imx_uart_dma_tx()
635 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
637 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
638 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
639 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
641 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
643 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
644 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
645 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
648 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
650 dev_err(dev, "DMA mapping error for TX.\n"); in imx_uart_dma_tx()
656 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
658 dev_err(dev, "We cannot prepare for the TX slave dma!\n"); in imx_uart_dma_tx()
661 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
662 desc->callback_param = sport; in imx_uart_dma_tx()
664 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", in imx_uart_dma_tx()
672 sport->dma_is_txing = 1; in imx_uart_dma_tx()
684 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
688 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
693 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
694 if (sport->tx_state == OFF) { in imx_uart_start_tx()
696 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
707 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && in imx_uart_start_tx()
708 !port->rs485_rx_during_tx_gpio) in imx_uart_start_tx()
711 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
713 if (port->rs485.delay_rts_before_send > 0) { in imx_uart_start_tx()
714 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
715 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
722 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
723 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
725 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
730 * tx-callback. in imx_uart_start_tx()
732 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
738 sport->tx_state = SEND; in imx_uart_start_tx()
741 sport->tx_state = SEND; in imx_uart_start_tx()
744 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
749 if (sport->dma_is_enabled) { in imx_uart_start_tx()
750 if (sport->port.x_char) { in imx_uart_start_tx()
751 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
752 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
760 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
775 * Update sport->old_status here, so any follow-up calls to in __imx_uart_rtsint()
783 * further TX transfers. in __imx_uart_rtsint()
786 sport->old_status |= TIOCM_CTS; in __imx_uart_rtsint()
788 sport->old_status &= ~TIOCM_CTS; in __imx_uart_rtsint()
789 uart_handle_cts_change(&sport->port, usr1); in __imx_uart_rtsint()
790 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
800 spin_lock(&sport->port.lock); in imx_uart_rtsint()
804 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
813 spin_lock(&sport->port.lock); in imx_uart_txint()
815 spin_unlock(&sport->port.lock); in imx_uart_txint()
853 * We count interrupts, not chars in 'idle-counter' for simplicity. in imx_uart_check_flood()
858 sport->idle_counter = 0; in imx_uart_check_flood()
859 } else if (++sport->idle_counter > 3) { in imx_uart_check_flood()
860 dev_warn(sport->port.dev, "RX flood detected: soft reset."); in imx_uart_check_flood()
861 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ in imx_uart_check_flood()
868 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
878 sport->port.icount.rx++; in __imx_uart_rxint()
882 sport->port.icount.brk++; in __imx_uart_rxint()
883 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
887 sport->port.icount.parity++; in __imx_uart_rxint()
889 sport->port.icount.frame++; in __imx_uart_rxint()
891 sport->port.icount.overrun++; in __imx_uart_rxint()
893 if (rx & sport->port.ignore_status_mask) in __imx_uart_rxint()
896 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
907 sport->port.sysrq = 0; in __imx_uart_rxint()
908 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { in __imx_uart_rxint()
912 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
916 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
929 spin_lock(&sport->port.lock); in imx_uart_rxint()
933 spin_unlock(&sport->port.lock); in imx_uart_rxint()
941 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
956 if (sport->dte_mode) in imx_uart_get_hwmctrl()
971 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
976 sport->old_status = status; in imx_uart_mctrl_check()
979 sport->port.icount.rng++; in imx_uart_mctrl_check()
981 sport->port.icount.dsr++; in imx_uart_mctrl_check()
983 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
985 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
987 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
996 spin_lock(&sport->port.lock); in imx_uart_int()
1061 sport->port.icount.overrun++; in imx_uart_int()
1066 spin_unlock(&sport->port.lock); in imx_uart_int()
1081 /* If the TX DMA is working, return 0. */ in imx_uart_tx_empty()
1082 if (sport->dma_is_txing) in imx_uart_tx_empty()
1094 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1105 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1118 * configured for CRTSCTS, so we use inverted UCR2_IRTS in imx_uart_set_mctrl()
1137 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1149 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1158 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1162 * This is our per-port timeout handler, for checking the
1170 if (sport->port.state) { in imx_uart_timeout()
1171 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1173 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1175 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1190 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1191 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1192 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1194 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1200 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1203 spin_lock(&sport->port.lock); in imx_uart_dma_rx_callback()
1205 spin_unlock(&sport->port.lock); in imx_uart_dma_rx_callback()
1210 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1213 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1215 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1221 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1224 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1225 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1227 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1228 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1231 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1234 spin_lock(&sport->port.lock); in imx_uart_dma_rx_callback()
1236 spin_unlock(&sport->port.lock); in imx_uart_dma_rx_callback()
1238 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1241 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1245 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1248 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1252 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1254 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1257 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1258 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1263 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1269 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1270 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1271 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1275 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1276 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1278 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1282 return -EINVAL; in imx_uart_start_rx_dma()
1286 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1292 return -EINVAL; in imx_uart_start_rx_dma()
1294 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1295 desc->callback_param = sport; in imx_uart_start_rx_dma()
1298 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1299 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1306 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1313 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1315 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1317 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1321 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1324 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1330 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1334 sport->idle_counter = 0; in imx_uart_clear_rx_errors()
1356 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1357 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1358 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1359 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1360 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1361 kfree(sport->rx_buf); in imx_uart_dma_exit()
1362 sport->rx_buf = NULL; in imx_uart_dma_exit()
1365 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1366 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1367 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1368 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1375 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1379 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1380 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1382 ret = -EINVAL; in imx_uart_dma_init()
1387 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1390 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1391 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1397 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1398 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1399 if (!sport->rx_buf) { in imx_uart_dma_init()
1400 ret = -ENOMEM; in imx_uart_dma_init()
1403 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1405 /* Prepare for TX : */ in imx_uart_dma_init()
1406 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1407 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1408 dev_err(dev, "cannot get the TX DMA channel!\n"); in imx_uart_dma_init()
1409 ret = -EINVAL; in imx_uart_dma_init()
1414 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1417 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1419 dev_err(dev, "error in TX dma configuration."); in imx_uart_dma_init()
1440 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1454 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1468 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1471 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1473 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1494 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1507 if (sport->have_rtscts) in imx_uart_startup()
1515 if (sport->inverted_rx) in imx_uart_startup()
1521 * configure tx polarity before enabling tx in imx_uart_startup()
1523 if (sport->inverted_tx) in imx_uart_startup()
1529 if (sport->dte_mode) in imx_uart_startup()
1537 if (!sport->have_rtscts) in imx_uart_startup()
1540 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1550 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1567 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1578 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1579 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1580 if (sport->dma_is_txing) { in imx_uart_shutdown()
1581 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1582 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1583 sport->dma_is_txing = 0; in imx_uart_shutdown()
1585 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1586 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1587 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1589 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1592 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1596 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1600 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1602 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1606 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1611 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1617 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1623 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_shutdown()
1624 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_shutdown()
1625 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_shutdown()
1639 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1641 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1642 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1649 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1651 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1654 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1655 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1656 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1659 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1664 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1679 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1687 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1688 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1689 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1690 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1694 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1699 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1702 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1712 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1715 if (!sport->have_rtscts) in imx_uart_set_termios()
1716 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1718 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1724 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1729 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1738 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1740 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1742 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1744 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1748 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1749 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1750 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1751 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1752 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1757 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1758 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1759 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1760 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1761 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1766 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1767 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1770 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1771 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1774 * Update the per-port timeout. in imx_uart_set_termios()
1776 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1778 /* custom-baudrate handling */ in imx_uart_set_termios()
1779 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1781 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1783 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1789 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1792 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1798 num -= 1; in imx_uart_set_termios()
1799 denom -= 1; in imx_uart_set_termios()
1822 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1827 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1828 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1830 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1835 return port->type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1844 port->type = PORT_IMX; in imx_uart_config_port()
1857 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1858 ret = -EINVAL; in imx_uart_verify_port()
1859 if (port->irq != ser->irq) in imx_uart_verify_port()
1860 ret = -EINVAL; in imx_uart_verify_port()
1861 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1862 ret = -EINVAL; in imx_uart_verify_port()
1863 if (port->uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1864 ret = -EINVAL; in imx_uart_verify_port()
1865 if (port->mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1866 ret = -EINVAL; in imx_uart_verify_port()
1867 if (port->iobase != ser->port) in imx_uart_verify_port()
1868 ret = -EINVAL; in imx_uart_verify_port()
1869 if (ser->hub6 != 0) in imx_uart_verify_port()
1870 ret = -EINVAL; in imx_uart_verify_port()
1883 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1886 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1888 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1892 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1920 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1961 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1962 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1963 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1964 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1965 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1969 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1976 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1977 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1978 rs485conf->flags & SER_RS485_RX_DURING_TX) { in imx_uart_rs485_config()
2031 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
2037 if (sport->port.sysrq) in imx_uart_console_write()
2040 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2042 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2059 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2070 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2110 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2112 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2127 *baud = (baud_raw + 50) / 100 * 100; in imx_uart_console_get_options()
2131 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2151 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2152 co->index = 0; in imx_uart_console_setup()
2153 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2155 return -ENODEV; in imx_uart_console_setup()
2158 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2169 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2172 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2176 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2178 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2187 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit()
2189 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2190 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2203 .index = -1,
2228 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2229 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2230 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2231 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2241 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2242 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2243 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2244 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2262 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2271 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2273 return -ENOMEM; in imx_uart_probe()
2275 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2279 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2282 sport->port.line = ret; in imx_uart_probe()
2284 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || in imx_uart_probe()
2285 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */ in imx_uart_probe()
2287 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); in imx_uart_probe()
2289 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); in imx_uart_probe()
2291 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); in imx_uart_probe()
2293 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); in imx_uart_probe()
2295 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2296 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2297 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2299 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2300 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2303 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2304 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2305 sport->port.line); in imx_uart_probe()
2306 return -EINVAL; in imx_uart_probe()
2319 sport->port.dev = &pdev->dev; in imx_uart_probe()
2320 sport->port.mapbase = res->start; in imx_uart_probe()
2321 sport->port.membase = base; in imx_uart_probe()
2322 sport->port.type = PORT_IMX; in imx_uart_probe()
2323 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2324 sport->port.irq = rxirq; in imx_uart_probe()
2325 sport->port.fifosize = 32; in imx_uart_probe()
2326 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2327 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2328 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2330 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2331 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2332 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2333 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2335 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2336 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2337 return PTR_ERR(sport->gpios); in imx_uart_probe()
2339 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2340 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2341 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2342 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2346 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2347 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2348 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2349 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2353 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2356 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2358 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); in imx_uart_probe()
2362 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2371 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2372 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2373 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2374 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2375 dev_err(&pdev->dev, in imx_uart_probe()
2376 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2398 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2399 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_probe()
2413 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2444 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2445 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2446 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2447 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2454 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2455 dev_name(&pdev->dev), sport); in imx_uart_probe()
2457 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2462 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2463 dev_name(&pdev->dev), sport); in imx_uart_probe()
2465 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2470 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2471 dev_name(&pdev->dev), sport); in imx_uart_probe()
2473 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2478 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2479 dev_name(&pdev->dev), sport); in imx_uart_probe()
2481 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2486 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2490 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2493 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2502 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2511 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2512 if (!sport->context_saved) { in imx_uart_restore_context()
2513 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2517 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2518 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2519 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2520 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2521 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2522 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2523 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2524 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2525 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2526 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2527 sport->context_saved = false; in imx_uart_restore_context()
2528 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2536 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2537 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2538 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2539 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2540 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2541 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2542 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2543 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2544 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2545 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2546 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2547 sport->context_saved = true; in imx_uart_save_context()
2548 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2564 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2582 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2596 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2610 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2611 disable_irq(sport->port.irq); in imx_uart_suspend()
2613 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2630 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2631 enable_irq(sport->port.irq); in imx_uart_resume()
2633 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2642 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2644 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2651 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2653 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2676 .name = "imx-uart",
2708 MODULE_ALIAS("platform:imx-uart");